Searched refs:base (Results 151 - 175 of 1118) sorted by relevance

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/drivers/scsi/
H A Daha1740.c216 static int aha1740_test_port(unsigned int base) argument
218 if ( inb(PORTADR(base)) & PORTADDR_ENH )
234 unsigned int base; local
243 base = host->io_port;
247 while(inb(G2STAT(base)) & G2STAT_INTPEND) {
250 adapstat = inb(G2INTST(base));
251 ecbptr = ecb_dma_to_cpu (host, inl(MBOXIN0(base)));
252 outb(G2CNTRL_IRST,G2CNTRL(base)); /* interrupt reset */
259 outb(G2CNTRL_HRDY,G2CNTRL(base));
262 inb(G2STAT(base)),adapsta
475 unsigned int base = SCpnt->device->host->io_port; local
510 aha1740_getconfig(unsigned int base, unsigned int *irq_level, unsigned int *irq_type, unsigned int *translation) argument
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H A Dlasi700.c101 unsigned long base = dev->hpa.start + LASI_SCSI_CORE_OFFSET; local
113 hostdata->base = ioremap_nocache(base, 0x100);
131 host->base = base;
146 iounmap(hostdata->base);
161 iounmap(hostdata->base);
/drivers/staging/usbip/
H A Dusbip_common.c297 pdu->base.command,
298 pdu->base.seqnum,
299 pdu->base.devid,
300 pdu->base.direction,
301 pdu->base.ep);
303 switch (pdu->base.command) {
499 static void correct_endian_basic(struct usbip_header_basic *base, int send) argument
502 base->command = cpu_to_be32(base->command);
503 base
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/drivers/gpu/drm/i915/
H A Di915_gem_tiling.c145 /* This is the base swizzling by the GPU for
262 if (INTEL_INFO(obj->base.dev)->gen >= 4)
265 if (INTEL_INFO(obj->base.dev)->gen == 3) {
277 if (INTEL_INFO(obj->base.dev)->gen == 3)
282 while (size < obj->base.size)
308 if (&obj->base == NULL)
312 args->stride, obj->base.size, args->tiling_mode)) {
313 drm_gem_object_unreference_unlocked(&obj->base);
318 drm_gem_object_unreference_unlocked(&obj->base);
363 (obj->gtt_offset + obj->base
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H A Dintel_dp.c47 struct intel_encoder base; member in struct:intel_dp
81 return intel_dp->base.type == INTEL_OUTPUT_EDP;
110 return container_of(encoder, struct intel_dp, base.base);
116 struct intel_dp, base);
146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
327 struct drm_device *dev = intel_dp->base.base.dev;
335 struct drm_device *dev = intel_dp->base.base
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/drivers/watchdog/
H A Dsp805_wdt.c60 * @base: base address of wdt
69 void __iomem *base; member in struct:sp805_wdt
116 load = readl_relaxed(wdt->base + WDTVALUE);
119 if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
131 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
132 writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
133 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
134 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
135 writel_relaxed(LOCK, wdt->base
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H A Dimx2_wdt.c63 void __iomem *base; member in struct:__anon5968
89 u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
100 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
104 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
109 __raw_writew(IMX2_WDT_SEQ1, imx2_wdt.base + IMX2_WDT_WSR);
110 __raw_writew(IMX2_WDT_SEQ2, imx2_wdt.base + IMX2_WDT_WSR);
143 u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
148 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
192 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WRSR);
266 imx2_wdt.base
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H A Djz4740_wdt.c68 void __iomem *base; member in struct:jz4740_wdt_drvdata
76 writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
102 writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
103 writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
105 writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
106 writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
108 drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
110 writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
129 writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
174 drvdata->base
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/drivers/ata/
H A Dpata_octeon_cf.c341 /* The base of the registers is at ioaddr.data_addr. */
342 void __iomem *base = ap->ioaddr.data_addr; local
344 blob = __raw_readw(base + 0xc);
347 blob = __raw_readw(base + 2);
351 blob = __raw_readw(base + 4);
355 blob = __raw_readw(base + 6);
363 blob = __raw_readw(base + 0xc);
366 blob = __raw_readw(base + 2);
370 blob = __raw_readw(base + 4);
385 void __iomem *base local
395 void __iomem *base = ap->ioaddr.data_addr; local
427 void __iomem *base = ap->ioaddr.data_addr; local
474 void __iomem *base = ap->ioaddr.data_addr; local
808 void __iomem *base; local
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/drivers/i2c/busses/
H A Di2c-via.c101 u16 base; local
114 base = PM_CFG_IOBASE0;
118 base = PM_CFG_IOBASE1;
122 base = PM_CFG_IOBASE1;
126 pci_read_config_word(dev, base, &pm_io_base);
H A Dscx200_acb.c48 static int base[MAX_DEVICES] = { 0x820, 0x840 }; variable
49 module_param_array(base, int, NULL, 0);
50 MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
78 unsigned base; member in struct:scx200_acb_iface
92 #define ACBSDA (iface->base + 0)
93 #define ACBST (iface->base + 1)
99 #define ACBCST (iface->base + 2)
101 #define ACBCTL1 (iface->base + 3)
107 #define ACBADDR (iface->base + 4)
108 #define ACBCTL2 (iface->base
484 scx200_create_dev(const char *text, unsigned long base, int index, struct device *dev) argument
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H A Di2c-parport-light.c44 static u16 base; variable
45 module_param(base, ushort, 0);
46 MODULE_PARM_DESC(base, "Base I/O address");
56 outb(d, base+p);
61 return inb(base+p);
237 if (base == 0) {
238 pr_info(DRVNAME ": using default base 0x%x\n", DEFAULT_BASE);
239 base = DEFAULT_BASE;
242 if (!request_region(base, 3, DRVNAME))
252 err = i2c_parport_device_add(base);
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/drivers/mmc/host/
H A Ds3cmci.c78 con = readl(host->base + S3C2410_SDICON);
79 pre = readl(host->base + S3C2410_SDIPRE);
80 cmdarg = readl(host->base + S3C2410_SDICMDARG);
81 cmdcon = readl(host->base + S3C2410_SDICMDCON);
82 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
83 r0 = readl(host->base + S3C2410_SDIRSP0);
84 r1 = readl(host->base + S3C2410_SDIRSP1);
85 r2 = readl(host->base + S3C2410_SDIRSP2);
86 r3 = readl(host->base + S3C2410_SDIRSP3);
87 timer = readl(host->base
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/drivers/rtc/
H A Drtc-88pm860x.c112 unsigned long ticks, base, data; local
117 base = (buf[1] << 24) | (buf[3] << 16) | (buf[5] << 8) | buf[7];
122 ticks = base + data;
123 dev_dbg(info->dev, "get base:0x%lx, RO count:0x%lx, ticks:0x%lx\n",
124 base, data, ticks);
135 unsigned long ticks, base, data; local
148 base = ticks - data;
149 dev_dbg(info->dev, "set base:0x%lx, RO count:0x%lx, ticks:0x%lx\n",
150 base, data, ticks);
152 pm860x_page_reg_write(info->i2c, REG0_DATA, (base >> 2
166 unsigned long ticks, base, data; local
191 unsigned long ticks, base, data; local
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/drivers/gpio/
H A Dgpiolib.c100 const int gpio = chip->base + offset;
129 int base = -ENOSPC; local
138 base = i;
148 if (gpio_is_valid(base))
149 pr_debug("%s: found new base at %d\n", __func__, base);
150 return base;
560 * /base ... matching gpio_chip.base (N)
570 return sprintf(buf, "%d\n", chip->base);
1042 int base = chip->base; local
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H A Dgpio-mxc.c61 void __iomem *base; member in struct:mxc_gpio_port
152 void __iomem *reg = port->base;
187 writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
194 void __iomem *reg = port->base;
243 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
258 irq_msk = readl(port->base + GPIO_IMR);
262 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
305 port->base, handle_level_irq);
383 port->base
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/drivers/gpu/drm/nouveau/
H A Dnv50_mpeg.c30 struct nouveau_exec_engine base; member in struct:nv50_mpeg_engine
232 pmpeg->base.destroy = nv50_mpeg_destroy;
233 pmpeg->base.init = nv50_mpeg_init;
234 pmpeg->base.fini = nv50_mpeg_fini;
235 pmpeg->base.context_new = nv50_mpeg_context_new;
236 pmpeg->base.context_del = nv50_mpeg_context_del;
237 pmpeg->base.object_new = nv50_mpeg_object_new;
238 pmpeg->base.tlb_flush = nv50_mpeg_tlb_flush;
242 NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
245 NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
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/drivers/gpu/drm/udl/
H A Dudl_gem.c22 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
46 ret = drm_gem_handle_create(file, &obj->base, &handle);
48 drm_gem_object_release(&obj->base);
53 drm_gem_object_unreference(&obj->base);
133 page_count = obj->base.size / PAGE_SIZE;
139 inode = obj->base.filp->f_path.dentry->d_inode;
161 int page_count = obj->base.size / PAGE_SIZE;
173 int page_count = obj->base.size / PAGE_SIZE;
228 if (!gobj->base.map_list.map) {
234 *offset = (u64)gobj->base
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/drivers/input/serio/
H A Dpcips2.c43 unsigned int base; member in struct:pcips2_data
53 stat = inb(ps2if->base + PS2_STATUS);
57 outb(val, ps2if->base + PS2_DATA);
71 status = inb(ps2if->base + PS2_STATUS);
75 scancode = inb(ps2if->base + PS2_DATA);
94 status = inb(ps2if->base + PS2_STATUS);
97 scancode = inb(ps2if->base + PS2_DATA);
108 outb(PS2_CTRL_ENABLE, ps2if->base);
116 outb(val, ps2if->base);
125 outb(0, ps2if->base);
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/drivers/mtd/onenand/
H A Dsamsung.c137 void __iomem *base; member in struct:s3c_onenand
161 return readl(onenand->base + offset);
166 writel(value, onenand->base + offset);
186 (unsigned int) onenand->base + i,
245 int reg = addr - this->base;
295 unsigned int reg = addr - this->base;
544 void __iomem *base = onenand->dma_addr; local
548 writel(src, base + S5PC110_DMA_SRC_ADDR);
549 writel(dst, base + S5PC110_DMA_DST_ADDR);
552 writel(S5PC110_DMA_SRC_CFG_READ, base
588 void __iomem *base = onenand->dma_addr; local
610 void __iomem *base = onenand->dma_addr; local
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/drivers/usb/gadget/
H A Dimx_udc.c56 int temp = __raw_readl(imx_usb->base + USB_CTRL);
58 imx_usb->base + USB_CTRL);
64 int temp = __raw_readl(imx_usb->base + USB_CTRL);
67 imx_usb->base + USB_CTRL);
75 int temp = __raw_readl(imx_usb->base + USB_ENAB);
78 __raw_writel(temp | ENAB_RST, imx_usb->base + USB_ENAB);
81 do {} while (__raw_readl(imx_usb->base + USB_ENAB) & ENAB_RST);
84 do {} while (!(__raw_readl(imx_usb->base + USB_DADR) & DADR_CFG));
96 do {} while (!(__raw_readl(imx_usb->base + USB_DADR) & DADR_CFG));
101 __raw_writeb(i, imx_usb->base
1413 void __iomem *base; local
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/drivers/gpu/drm/radeon/
H A Datom.c102 static uint32_t atom_iio_execute(struct atom_context *ctx, int base, argument
109 switch (CU8(base)) {
111 base++;
114 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));
115 base += 3;
119 (void)ctx->card->ioreg_read(ctx->card, CU16(base + 1));
120 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
121 base += 3;
125 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
126 CU8(base
1161 int base = CU16(ctx->cmd_table + 4 + 2 * index); local
1238 atom_index_iio(struct atom_context *ctx, int base) argument
1252 int base; local
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/drivers/isdn/hardware/avm/
H A Dt1isa.c62 static int t1_detectandinit(unsigned int base, unsigned irq, int cardnr) argument
87 t1outp(base, T1_RESETBOARD, 0xf);
89 dummy = t1inp(base, T1_FASTLINK + T1_OUTSTAT); /* first read */
92 dummy = (base >> 4) & 0xff;
93 for (i = 1; i <= 0xf; i++) t1outp(base, i, dummy);
94 t1outp(base, HEMA_PAL_ID & 0xf, dummy);
95 t1outp(base, HEMA_PAL_ID >> 4, cregs[0]);
96 for (i = 1; i < 7; i++) t1outp(base, 0, cregs[i]);
97 t1outp(base, ((base >>
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/drivers/video/
H A Dsh7760fb.c34 void __iomem *base; member in struct:sh7760fb_par
63 while (--i && ((ioread16(par->base + LDPMMR) & 3) != val))
77 unsigned short cntr = ioread16(par->base + LDCNTR);
78 unsigned short intr = ioread16(par->base + LDINTR);
94 iowrite16(intr, par->base + LDINTR);
95 iowrite16(cntr, par->base + LDCNTR);
252 iowrite16(par->pd->ldickr, par->base + LDICKR); /* pixclock */
253 iowrite16(ldmtr, par->base + LDMTR); /* polarities */
254 iowrite16(lddfr, par->base + LDDFR); /* color/depth */
255 iowrite16((par->rot ? 1 << 13 : 0), par->base
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/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_resource.c35 struct ttm_base_object base; member in struct:vmw_user_context
40 struct ttm_base_object base; member in struct:vmw_user_surface
46 struct ttm_base_object base; member in struct:vmw_user_dma_buffer
61 struct ttm_base_object base; member in struct:vmw_user_stream
79 return container_of(bo, struct vmw_dma_buffer, base);
361 * base object. It releases the base-object's reference on the resource object.
366 struct ttm_base_object *base = *p_base; local
368 container_of(base, struct vmw_user_context, base);
1224 struct ttm_base_object *base; local
1259 struct ttm_base_object *base = *p_base; local
1468 struct ttm_base_object *base; local
1514 struct ttm_base_object *base; local
1584 struct ttm_base_object *base = *p_base; local
1685 struct ttm_base_object *base; local
1778 struct ttm_base_object *base = *p_base; local
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