/drivers/gpu/drm/i915/ |
H A D | i915_gem.c | 207 ret = drm_gem_handle_create(file, &obj->base, &handle); 209 drm_gem_object_release(&obj->base); 210 i915_gem_info_remove_obj(dev->dev_private, obj->base.size); 216 drm_gem_object_unreference(&obj->base); 256 drm_i915_private_t *dev_priv = obj->base.dev->dev_private; 273 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; 386 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; 489 if (&obj->base == NULL) { 495 if (args->offset > obj->base.size || 496 args->size > obj->base [all...] |
/drivers/gpu/drm/radeon/ |
H A D | radeon_connectors.c | 191 if (conflict->encoder_ids[i] == encoder->base.id) { 324 radeon_property_change_mode(&radeon_encoder->base); 338 radeon_property_change_mode(&radeon_encoder->base); 352 radeon_property_change_mode(&radeon_encoder->base); 366 radeon_property_change_mode(&radeon_encoder->base); 391 radeon_property_change_mode(&radeon_encoder->base); 427 radeon_property_change_mode(&radeon_encoder->base); 559 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 614 radeon_property_change_mode(&radeon_encoder->base); 680 radeon_connector->edid = drm_get_edid(&radeon_connector->base, [all...] |
/drivers/ata/ |
H A D | sata_vsc.c | 55 /* Interrupt register offsets (from chip base address) */ 74 /* DMA base */ 79 /* SCRs base */ 316 void __iomem *base) 318 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; 319 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; 320 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET; 321 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET; 322 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET; 323 port->lbal_addr = base 315 vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base) argument [all...] |
H A D | pata_cs5530.c | 61 void __iomem *base = cs5530_port_base(ap); local 66 tuning = ioread32(base + 0x04); 71 base += 0x08; 73 iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); 88 void __iomem *base = cs5530_port_base(ap); local 93 tuning = ioread32(base + 0x04); 114 iowrite32(timing, base + 0x04); 120 iowrite32(tuning, base + 0x04); 121 iowrite32(timing, base + 0x0C);
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/drivers/gpio/ |
H A D | gpio-langwell.c | 245 u32 base, gpio, mask; local 250 for (base = 0; base < lnw->chip.ngpio; base += 32) { 251 gedr = gpio_reg(&lnw->chip, base, GEDR); 259 generic_handle_irq(lnw->irq_base + base + gpio); 302 void *base; local 322 base = ioremap_nocache(start, len); 323 if (!base) { 327 irq_base = *(u32 *)base; [all...] |
H A D | gpio-twl4030.c | 156 u8 base = REG_GPIODATADIR1 + d_bnk; local 160 ret = gpio_twl4030_read(base); 167 ret = gpio_twl4030_write(base, reg); 177 u8 base = 0; local 180 base = REG_SETGPIODATAOUT1 + d_bnk; 182 base = REG_CLEARGPIODATAOUT1 + d_bnk; 184 return gpio_twl4030_write(base, d_msk); 191 u8 base = 0; local 198 base = REG_GPIODATAIN1 + d_bnk; 199 ret = gpio_twl4030_read(base); [all...] |
/drivers/parport/ |
H A D | parport_sunbpp.c | 52 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 62 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 72 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 80 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 88 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 108 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 131 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 159 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 218 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 228 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; 295 void __iomem *base; local [all...] |
H A D | parport_gsc.h | 59 #define EPPDATA(p) ((p)->base + 0x4) 60 #define EPPADDR(p) ((p)->base + 0x3) 61 #define CONTROL(p) ((p)->base + 0x2) 62 #define STATUS(p) ((p)->base + 0x1) 63 #define DATA(p) ((p)->base + 0x0) 217 extern struct parport *parport_gsc_probe_port(unsigned long base,
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/drivers/scsi/aic7xxx/ |
H A D | aic79xx_osm_pci.c | 252 ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, resource_size_t *base, argument 255 *base = pci_resource_start(ahd->dev_softc, 0); 262 if (*base == 0 || *base2 == 0) 264 if (!request_region(*base, 256, "aic79xx")) 267 release_region(*base, 256); 313 resource_size_t base; local 322 base = 0; 324 error = ahd_linux_pci_reserve_mem_region(ahd, &base, &maddr); 326 ahd->platform_data->mem_busaddr = base; 354 (unsigned long long)base); [all...] |
H A D | aic7xxx_osm_pci.c | 347 ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, resource_size_t *base) argument 352 *base = pci_resource_start(ahc->dev_softc, 0); 353 if (*base == 0) 355 if (!request_region(*base, 256, "aic7xxx")) 390 resource_size_t base; local 399 base = 0; 401 error = ahc_linux_pci_reserve_mem_region(ahc, &base, &maddr); 403 ahc->platform_data->mem_busaddr = base; 433 (unsigned long long)base); 441 error = ahc_linux_pci_reserve_io_region(ahc, &base); [all...] |
/drivers/isdn/hisax/ |
H A D | bkm_a8.c | 80 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80)); 86 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value); 92 readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); 98 writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); 105 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0))); 111 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value); 119 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 127 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \ 129 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \ 131 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \ [all...] |
/drivers/mmc/host/ |
H A D | mxcmmc.c | 118 void __iomem *base; member in struct:mxcmci_host 205 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK); 207 host->base + MMC_REG_STR_STP_CLK); 210 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 212 writew(0xff, host->base + MMC_REG_RES_TO); 231 writew(nob, host->base + MMC_REG_NOB); 232 writew(blksz, host->base + MMC_REG_BLK_LEN); 313 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 316 writew(cmd->opcode, host->base + MMC_REG_CMD); 317 writel(cmd->arg, host->base [all...] |
/drivers/net/ethernet/calxeda/ |
H A D | xgmac.c | 377 void __iomem *base; member in struct:xgmac_priv 524 xgmac_dma_flush_tx_fifo(priv->base); 647 writel(flow, priv->base + XGMAC_FLOW_CTRL); 649 reg = readl(priv->base + XGMAC_OMR); 651 writel(reg, priv->base + XGMAC_OMR); 653 writel(0, priv->base + XGMAC_FLOW_CTRL); 655 reg = readl(priv->base + XGMAC_OMR); 657 writel(reg, priv->base + XGMAC_OMR); 758 writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR); 759 writel(priv->dma_rx_phy, priv->base 1448 void __iomem *base = priv->base; local [all...] |
/drivers/dma/ |
H A D | sa11x0-dma.c | 106 void __iomem *base; member in struct:sa11x0_dma_phy 126 void __iomem *base; member in struct:sa11x0_dma_dev 172 void __iomem *base = p->base; local 179 dcsr = readl_relaxed(base + DMA_DCSR_R); 216 writel_relaxed(sg->addr, base + dbsx); 217 writel_relaxed(sg->len, base + dbtx); 218 writel(dcsr, base + DMA_DCSR_S); 259 dcsr = readl_relaxed(p->base + DMA_DCSR_R); 265 p->base [all...] |
/drivers/gpu/drm/nouveau/ |
H A D | nv31_mpeg.c | 30 struct nouveau_exec_engine base; member in struct:nv31_mpeg_engine 141 pmpeg->base.set_tile_region(dev, i); 178 u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); local 188 nv_wr32(dev, 0x00b334, base); 194 nv_wr32(dev, 0x00b360, base); 201 nv_wr32(dev, 0x00b370, base); 312 pmpeg->base.destroy = nv31_mpeg_destroy; 313 pmpeg->base.init = nv31_mpeg_init; 314 pmpeg->base.fini = nv31_mpeg_fini; 316 pmpeg->base [all...] |
H A D | nv50_cursor.c | 39 struct drm_device *dev = nv_crtc->base.dev; 74 struct drm_device *dev = nv_crtc->base.dev; 108 struct drm_device *dev = nv_crtc->base.dev; 120 NV_DEBUG_KMS(nv_crtc->base.dev, "\n");
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/drivers/hwmon/ |
H A D | exynos4_tmu.c | 75 void __iomem *base; member in struct:exynos4_tmu_data 156 status = readb(data->base + EXYNOS4_TMU_REG_STATUS); 163 trim_info = readl(data->base + EXYNOS4_TMU_REG_TRIMINFO); 174 data->base + EXYNOS4_TMU_REG_THRESHOLD_TEMP); 177 data->base + EXYNOS4_TMU_REG_TRIG_LEVEL0); 179 data->base + EXYNOS4_TMU_REG_TRIG_LEVEL1); 181 data->base + EXYNOS4_TMU_REG_TRIG_LEVEL2); 183 data->base + EXYNOS4_TMU_REG_TRIG_LEVEL3); 186 data->base + EXYNOS4_TMU_REG_INTCLEAR); 215 writel(interrupt_en, data->base [all...] |
H A D | hwmon.c | 82 u16 base; local 92 pci_read_config_word(sb, 0x64, &base); 94 if (base == 0 && !(enable & BIT(2))) {
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/drivers/spi/ |
H A D | spi-davinci.c | 131 void __iomem *base; member in struct:davinci_spi 241 iowrite16(spidat1, dspi->base + SPIDAT1 + 2); 378 iowrite32(delay, dspi->base + SPIDELAY); 381 iowrite32(spifmt, dspi->base + SPIFMT0); 408 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); 413 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); 416 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 418 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 473 buf = ioread32(dspi->base + SPIBUF); 480 status = ioread32(dspi->base [all...] |
/drivers/gpu/drm/exynos/ |
H A D | exynos_drm_plane.c | 20 struct drm_plane base; member in struct:exynos_plane 41 container_of(plane, struct exynos_plane, base); 77 container_of(plane, struct exynos_plane, base); 97 container_of(plane, struct exynos_plane, base); 126 return drm_plane_init(dev, &exynos_plane->base, possible_crtcs, 164 exynos_plane = container_of(plane, struct exynos_plane, base);
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/drivers/ide/ |
H A D | ide_platform.c | 26 void __iomem *base, 31 unsigned long port = (unsigned long)base; 54 void __iomem *base, *alt_base; local 84 base = devm_ioremap(&pdev->dev, 89 base = devm_ioport_map(&pdev->dev, 96 plat_ide_setup_ports(&hw, base, alt_base, pdata, res_irq->start); 25 plat_ide_setup_ports(struct ide_hw *hw, void __iomem *base, void __iomem *ctrl, struct pata_platform_info *pdata, int irq) argument
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/drivers/video/ |
H A D | sh_mipi_dsi.c | 57 void __iomem *base; member in struct:sh_mipi 133 void __iomem *base = mipi->base; local 243 iowrite32(0x00000001, base + SYSCTRL); 246 iowrite32(0x00000000, base + SYSCTRL); 257 iowrite32(0x70003332, base + TIMSET); 259 iowrite32(0x00000000, base + RESREQSET0); 261 iowrite32(0x00000100, base + RESREQSET1); 263 iowrite32(0x0fffffff, base + HSTTOVSET); 265 iowrite32(0x0fffffff, base [all...] |
/drivers/scsi/ |
H A D | ppa.c | 28 static void ppa_reset_pulse(unsigned int base); 32 int base; /* Actual port address */ member in struct:__anon4837 56 dev->base = dev->dev->port->base; 198 unsigned short ppb = dev->base; 256 static int ppa_byte_out(unsigned short base, const char *buffer, int len) argument 261 w_dtr(base, *buffer++); 262 w_ctr(base, 0xe); 263 w_ctr(base, 0xc); 268 static int ppa_byte_in(unsigned short base, cha argument 280 ppa_nibble_in(unsigned short base, char *buffer, int len) argument 868 ppa_reset_pulse(unsigned int base) argument [all...] |
/drivers/mfd/ |
H A D | jz4740-adc.c | 57 void __iomem *base; member in struct:jz4740_adc 106 val = readb(adc->base + JZ_REG_ADC_ENABLE); 111 writeb(val, adc->base + JZ_REG_ADC_ENABLE); 147 cfg = readl(adc->base + JZ_REG_ADC_CFG); 152 writel(cfg, adc->base + JZ_REG_ADC_CFG); 230 dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret); 250 adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); 251 if (!adc->base) { 269 gc = irq_alloc_generic_chip("INTC", 1, irq_base, adc->base, 286 writeb(0x00, adc->base [all...] |
/drivers/watchdog/ |
H A D | mpcore_wdt.c | 44 void __iomem *base; member in struct:mpcore_wdt 82 if (readl(wdt->base + TWD_WDOG_INTSTAT)) { 86 writel(1, wdt->base + TWD_WDOG_INTSTAT); 105 count = __raw_readl(wdt->base + TWD_WDOG_COUNTER); 110 writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD); 118 writel(0x12345678, wdt->base + TWD_WDOG_DISABLE); 119 writel(0x87654321, wdt->base + TWD_WDOG_DISABLE); 120 writel(0x0, wdt->base + TWD_WDOG_CONTROL); 133 writel(0x0000FF01, wdt->base + TWD_WDOG_CONTROL); 136 writel(0x0000FF09, wdt->base [all...] |