/drivers/gpu/drm/radeon/ |
H A D | radeon.h | 205 dma_addr_t addr; member in struct:radeon_dummy_page 699 unsigned pfn, uint64_t addr, uint32_t flags); 1163 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
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H A D | radeon_atombios.c | 575 uint8_t *addr = (uint8_t *) path_obj->asDispPath; local 577 addr += path_size; 578 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 1993 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2198 info.addr = controller->ucI2cAddress >> 1;
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H A D | radeon_combios.c | 2618 info.addr = i2c_addr >> 1; 2635 info.addr = 0x28; 2639 name, info.addr); 2936 uint32_t addr = (RBIOS16(offset) & 0x1fff); local 2945 WREG32(addr, val); 2950 WREG32(addr, val); 2957 tmp = RREG32(addr); 2960 WREG32(addr, tmp); 2967 tmp = RREG32(addr); 2970 WREG32(addr, tm 3015 uint8_t addr = (RBIOS8(offset) & 0x3f); local 3151 uint32_t addr = 0; local [all...] |
H A D | radeon_cp.c | 121 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr) argument 125 if (addr < 0x10000) 126 ret = DRM_READ32(dev_priv->mmio, addr); 128 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr); 135 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) argument 138 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); 144 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) argument 147 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); 153 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) argument 156 RADEON_WRITE(RS690_MC_INDEX, (addr 162 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) argument 171 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) argument 297 RADEON_READ_PLL(struct drm_device * dev, int addr) argument 305 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) argument [all...] |
H A D | radeon_gart.c | 161 rdev->gart.pages_addr[p] = rdev->dummy_page.addr; 260 rdev->gart.pages_addr[i] = rdev->dummy_page.addr; 524 u64 addr = 0; local 528 addr = (mem->start << PAGE_SHIFT); 529 addr += pfn * RADEON_GPU_PAGE_SIZE; 530 addr += rdev->vm_manager.vram_base_offset; 534 addr = mem->start << PAGE_SHIFT; 535 addr += pfn * RADEON_GPU_PAGE_SIZE; 536 addr = addr >> PAGE_SHIF 556 uint64_t addr = 0, pfn; local [all...] |
H A D | radeon_i2c.c | 49 .addr = DDC_ADDR, 55 .addr = DDC_ADDR, 461 WREG32(i2c_data, (p->addr << 1) & 0xff); 494 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 521 WREG32(i2c_data, (p->addr << 1) & 0xff); 667 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 711 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 751 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 1074 u8 addr, 1081 .addr 1072 radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, u8 slave_addr, u8 addr, u8 *val) argument 1106 radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, u8 slave_addr, u8 addr, u8 val) argument [all...] |
H A D | radeon_legacy_tv.c | 299 uint16_t addr, uint32_t value) 308 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 309 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); 321 static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) 328 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 329 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); 298 radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr, uint32_t value) argument
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H A D | rs400.c | 212 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) argument 221 entry = (lower_32_bits(addr) & PAGE_MASK) | 222 ((upper_32_bits(addr) & 0xff) << 4) |
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H A D | rs600.c | 534 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) argument 541 addr = addr & 0xFFFFFFFFFFFFF000ULL; 542 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 543 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 544 writeq(addr, ptr + (i * 8));
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H A D | si.c | 1890 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; local 1907 radeon_ring_write(ring, addr & 0xffffffff); 1908 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2520 (u32)(rdev->dummy_page.addr >> 12)); 2547 (u32)(rdev->dummy_page.addr >> 12));
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/drivers/gpu/drm/savage/ |
H A D | savage_state.c | 82 uint32_t addr) 84 if ((addr & 6) != 2) { /* reserved bits */ 85 DRM_ERROR("bad texAddr%d %08x (reserved bits)\n", unit, addr); 88 if (!(addr & 1)) { /* local */ 89 addr &= ~7; 90 if (addr < dev_priv->texture_offset || 91 addr >= dev_priv->texture_offset + dev_priv->texture_size) { 93 ("bad texAddr%d %08x (local addr out of range)\n", 94 unit, addr); 100 unit, addr); 81 savage_verify_texaddr(drm_savage_private_t * dev_priv, int unit, uint32_t addr) argument [all...] |
/drivers/gpu/drm/ttm/ |
H A D | ttm_bo_util.c | 189 void *addr; local 198 if (mem->bus.addr) { 199 addr = mem->bus.addr; 202 addr = ioremap_wc(mem->bus.base + mem->bus.offset, mem->bus.size); 204 addr = ioremap_nocache(mem->bus.base + mem->bus.offset, mem->bus.size); 205 if (!addr) { 212 *virtual = addr; 223 if (virtual && mem->bus.addr == NULL) 490 if (bo->mem.bus.addr) { [all...] |
/drivers/gpu/drm/via/ |
H A D | via_dma.c | 482 uint32_t addr, uint32_t *cmd_addr_hi, 500 cmd_addr = (addr) ? addr : 481 via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type, uint32_t addr, uint32_t *cmd_addr_hi, uint32_t *cmd_addr_lo, int skip_wait) argument
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H A D | via_verifier.c | 305 uint32_t *addr, *pitch, *height, tex; local 314 addr = 320 tmp = *addr++; 889 uint32_t addr, count, i; local 892 addr = *buf++ & ~VIA_VIDEOMASK; 896 VIA_WRITE(addr, *buf++); 945 uint32_t addr, count, i; local 951 addr = *buf++; 952 VIA_WRITE(addr, *buf++);
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/drivers/gpu/ion/ |
H A D | ion.c | 466 ion_phys_addr_t *addr, size_t *len) 486 ret = buffer->heap->ops->phys(buffer->heap, buffer, addr, len); 465 ion_phys(struct ion_client *client, struct ion_handle *handle, ion_phys_addr_t *addr, size_t *len) argument
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H A D | ion_carveout_heap.c | 50 void ion_carveout_free(struct ion_heap *heap, ion_phys_addr_t addr, argument 56 if (addr == ION_CARVEOUT_ALLOCATE_FAIL) 58 gen_pool_free(carveout_heap->pool, addr, size); 63 ion_phys_addr_t *addr, size_t *len) 65 *addr = buffer->priv_phys; 61 ion_carveout_heap_phys(struct ion_heap *heap, struct ion_buffer *buffer, ion_phys_addr_t *addr, size_t *len) argument
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H A D | ion_system_heap.c | 103 void *addr = vmap(&sub_page, 1, VM_MAP, local 105 memset(addr, 0, PAGE_SIZE); 106 vunmap(addr); 292 unsigned long addr = vma->vm_start; local 302 remap_pfn_range(vma, addr, page_to_pfn(sg_page(sg)), 304 addr += sg_dma_len(sg); 305 if (addr >= vma->vm_end) 410 ion_phys_addr_t *addr, size_t *len) 412 *addr = virt_to_phys(buffer->priv_virt); 408 ion_system_contig_heap_phys(struct ion_heap *heap, struct ion_buffer *buffer, ion_phys_addr_t *addr, size_t *len) argument
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/drivers/hv/ |
H A D | hv.c | 266 unsigned long addr; local 271 addr = (unsigned long)kmalloc(sizeof(struct aligned_input), GFP_ATOMIC); 272 if (!addr) 276 (ALIGN(addr, HV_HYPERCALL_PARAM_ALIGN)); 286 kfree((void *)addr);
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/drivers/hwmon/ |
H A D | abituguru.c | 211 unsigned short addr; /* uguru base address */ member in struct:abituguru_data 269 while (inb_p(data->addr + ABIT_UGURU_DATA) != state) { 292 outb(0x00, data->addr + ABIT_UGURU_DATA); 302 while (inb_p(data->addr + ABIT_UGURU_CMD) != 0xAC) { 317 while (inb_p(data->addr + ABIT_UGURU_DATA) != ABIT_UGURU_STATUS_INPUT) { 353 outb(bank_addr, data->addr + ABIT_UGURU_DATA); 358 * and send the sensor addr 376 outb(sensor_addr, data->addr + ABIT_UGURU_CMD); 404 buf[i] = inb(data->addr + ABIT_UGURU_CMD); 440 outb(buf[i], data->addr [all...] |
H A D | abituguru3.c | 158 unsigned short addr; /* uguru base address */ member in struct:abituguru3_data 649 while ((x = inb_p(data->addr + ABIT_UGURU3_DATA)) & 670 while (!((x = inb_p(data->addr + ABIT_UGURU3_DATA)) & 700 outb(0x20, data->addr + ABIT_UGURU3_DATA); 708 outb(0x10, data->addr + ABIT_UGURU3_CMD); 716 outb(0x00, data->addr + ABIT_UGURU3_CMD); 731 while ((x = inb(data->addr + ABIT_UGURU3_CMD)) != 0xAC) { 757 outb(0x1A, data->addr + ABIT_UGURU3_DATA); 766 outb(bank, data->addr + ABIT_UGURU3_CMD); 775 outb(offset, data->addr [all...] |
H A D | dme1737.c | 214 unsigned int addr; /* for ISA devices only */ member in struct:dme1737_data 575 outb(reg, data->addr); 576 val = inb(data->addr + 1); 596 outb(reg, data->addr); 597 outb(val, data->addr + 1); 2280 * these functions are used for addr enable/select. 2282 if (client->addr == 0x2e) 2392 u16 addr; local 2411 addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2413 if (!addr) { 2556 dme1737_isa_detect(int sio_cip, unsigned short *addr) argument 2597 dme1737_isa_device_add(unsigned short addr) argument 2766 unsigned short addr; local [all...] |
H A D | f71805f.c | 170 unsigned short addr; member in struct:f71805f_data 302 outb(reg, data->addr + ADDR_REG_OFFSET); 303 return inb(data->addr + DATA_REG_OFFSET); 309 outb(reg, data->addr + ADDR_REG_OFFSET); 310 outb(val, data->addr + DATA_REG_OFFSET); 322 outb(reg, data->addr + ADDR_REG_OFFSET); 323 val = inb(data->addr + DATA_REG_OFFSET) << 8; 324 outb(++reg, data->addr + ADDR_REG_OFFSET); 325 val |= inb(data->addr + DATA_REG_OFFSET); 333 outb(reg, data->addr [all...] |
H A D | f71882fg.c | 234 unsigned short addr; member in struct:f71882fg_data 1125 outb(reg, data->addr + ADDR_REG_OFFSET); 1126 val = inb(data->addr + DATA_REG_OFFSET); 1143 outb(reg, data->addr + ADDR_REG_OFFSET); 1144 outb(val, data->addr + DATA_REG_OFFSET); 2281 data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
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H A D | f75375s.c | 96 unsigned short addr; member in struct:f75375_data
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H A D | it87.c | 243 unsigned short addr; member in struct:it87_data 1843 data->addr = res->start; 1981 release_region(data->addr, IT87_EC_EXTENT); 1995 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 1996 return inb_p(data->addr + IT87_DATA_REG_OFFSET); 2006 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 2007 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
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