/drivers/gpio/ |
H A D | gpio-tps65912.c | 32 int val; local 34 val = tps65912_reg_read(tps65912, TPS65912_GPIO1 + offset); 36 if (val & GPIO_STS_MASK)
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H A D | gpio-ucb1400.c | 25 static int ucb1400_gpio_dir_out(struct gpio_chip *gc, unsigned off, int val) argument 30 ucb1400_gpio_set_value(gpio->ac97, off, val); 41 static void ucb1400_gpio_set(struct gpio_chip *gc, unsigned off, int val) argument 45 ucb1400_gpio_set_value(gpio->ac97, off, val);
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H A D | gpio-vx855.c | 149 int val) 162 if (val) 167 if (val) 177 unsigned int nr, int val) 186 vx855gpio_set(gpio, nr, val); 148 vx855gpio_set(struct gpio_chip *gpio, unsigned int nr, int val) argument 176 vx855gpio_direction_output(struct gpio_chip *gpio, unsigned int nr, int val) argument
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H A D | gpio-wm831x.c | 42 int val = WM831X_GPN_DIR; local 45 val |= WM831X_GPN_TRI; 49 WM831X_GPN_FN_MASK, val); 82 int val = 0; local 86 val |= WM831X_GPN_TRI; 90 WM831X_GPN_FN_MASK, val);
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H A D | gpio-xilinx.c | 55 * @val: Value to be written to specified signal. 60 static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) argument 70 if (val) 110 * @val: Value to be written to specified signal. 116 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) argument 126 if (val)
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/drivers/gpu/drm/ |
H A D | ati_pcigart.c | 166 u32 val; local 170 val = page_base | 0xc; 173 val = (page_base >> 8) | 0xc; 177 val = page_base; 182 pci_gart[gart_idx] = cpu_to_le32(val); 184 DRM_WRITE32(map, gart_idx * sizeof(u32), val);
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H A D | drm_crtc.c | 43 char *fnname(int val) \ 47 if (list[i].type == val) \ 2819 struct drm_property *property, uint64_t *val) 2825 *val = connector->property_values[i]; 2818 drm_connector_property_get_value(struct drm_connector *connector, struct drm_property *property, uint64_t *val) argument
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/drivers/gpu/drm/exynos/ |
H A D | exynos_drm_fimd.c | 198 u32 val; local 209 val = VIDTCON0_VBPD(timing->upper_margin - 1) | 212 writel(val, ctx->regs + VIDTCON0); 215 val = VIDTCON1_HBPD(timing->left_margin - 1) | 218 writel(val, ctx->regs + VIDTCON1); 221 val = VIDTCON2_LINEVAL(timing->yres - 1) | 223 writel(val, ctx->regs + VIDTCON2); 226 val = ctx->vidcon0; 227 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); 230 val | 245 u32 val; local 272 u32 val; local 354 unsigned long val; local 432 unsigned long val, alpha, size; local 543 u32 val; local 639 u32 val; local 734 u32 val; local [all...] |
H A D | exynos_hdmi.c | 1197 u32 val = hdmi_reg_read(hdata, HDMI_HPD_STATUS); local 1199 if (val) 1384 u32 val; local 1426 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01; 1427 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val); 1609 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS); local 1610 if (val & HDMI_PHY_STATUS_READY) 1776 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0); local 1777 if (val & HDMI_PHY_STATUS_READY)
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H A D | exynos_mixer.c | 122 u32 val) 124 writel(val, res->vp_regs + reg_id); 128 u32 val, u32 mask) 132 val = (val & mask) | (old & ~mask); 133 writel(val, res->vp_regs + reg_id); 142 u32 val) 144 writel(val, res->mixer_regs + reg_id); 148 u32 reg_id, u32 val, u32 mask) 152 val 121 vp_reg_write(struct mixer_resources *res, u32 reg_id, u32 val) argument 127 vp_reg_writemask(struct mixer_resources *res, u32 reg_id, u32 val, u32 mask) argument 141 mixer_reg_write(struct mixer_resources *res, u32 reg_id, u32 val) argument 147 mixer_reg_writemask(struct mixer_resources *res, u32 reg_id, u32 val, u32 mask) argument 229 u32 val = (data[0] << 24) | (data[1] << 16) | local 260 u32 val; local 284 u32 val; local 325 u32 val = enable ? ~0 : 0; local 363 u32 val; local 493 u32 val; local 776 u32 val, val_base; local 818 u32 val; /* value stored to register */ local [all...] |
H A D | regs-mixer.h | 68 #define MXR_MASK_VAL(val, high_bit, low_bit) \ 69 (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit))
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H A D | regs-vp.h | 58 #define VP_MASK_VAL(val, high_bit, low_bit) \ 59 (((val) << (low_bit)) & VP_MASK(high_bit, low_bit))
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/drivers/gpu/drm/gma500/ |
H A D | cdv_intel_display.c | 135 static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) argument 157 *val = REG_READ(SB_DATA); 162 static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) argument 171 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val); 181 REG_WRITE(SB_DATA, val);
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H A D | intel_gmbus.c | 83 u32 val; 88 val = REG_READ(DSPCLK_GATE_D); 90 val |= DPCUNIT_CLOCK_GATE_DISABLE; 92 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 93 REG_WRITE(DSPCLK_GATE_D, val); 278 u32 val, loop = 0; local 285 val = REG_READ(GMBUS3 + reg_offset); 287 *buf++ = val & 0xff; 288 val >>= 8; 292 u32 val, loo local [all...] |
H A D | intel_i2c.c | 37 u32 val; local 39 val = REG_READ(chan->reg); 40 return (val & GPIO_CLOCK_VAL_IN) != 0; 47 u32 val; local 49 val = REG_READ(chan->reg); 50 return (val & GPIO_DATA_VAL_IN) != 0;
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H A D | mdfld_dsi_dpi.c | 473 u32 val; local 485 val = lane_count; 486 val |= dsi_config->channel_num << DSI_DPI_VIRT_CHANNEL_OFFSET; 490 val |= DSI_DPI_COLOR_FORMAT_RGB565; 493 val |= DSI_DPI_COLOR_FORMAT_RGB666; 496 val |= DSI_DPI_COLOR_FORMAT_RGB888; 502 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val); local 546 val = dsi_config->video_mode | DSI_DPI_COMPLETE_LAST_LINE; 547 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val); local
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H A D | mdfld_dsi_output.c | 252 uint64_t val; local 268 if (drm_connector_property_get_value(connector, property, &val)) 271 if (val == value) 278 centerechange = (val == DRM_MODE_SCALE_NO_SCALE) ||
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H A D | mdfld_dsi_output.h | 45 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 46 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) 47 #define FLD_MOD(orig, val, start, end) \ 48 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) 50 #define REG_FLD_MOD(reg, val, start, end) \ 51 REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end)) 54 u32 val, int start, int end) 58 while (FLD_GET(REG_READ(reg), start, end) != val) { 53 REGISTER_FLD_WAIT(struct drm_device *dev, u32 reg, u32 val, int start, int end) argument [all...] |
H A D | mdfld_dsi_pkg_sender.c | 233 u32 val; local 246 val = FLD_VAL(param, 23, 16) | FLD_VAL(cmd, 15, 8) | 249 REG_WRITE(ctrl_reg, val); 260 u32 val; local 310 val = FLD_VAL(len, 23, 8) | FLD_VAL(virtual_channel, 7, 6) | 313 REG_WRITE(ctrl_reg, val);
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H A D | oaktrail_hdmi.c | 34 #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
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H A D | oaktrail_hdmi_i2c.c | 36 #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg)) 265 DRM_DEBUG_DRIVER("old gpio val %x\n", temp); 268 DRM_DEBUG_DRIVER("new gpio val %x\n", temp);
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H A D | psb_drv.h | 942 uint32_t val) 945 iowrite32((val), dev_priv->vdc_reg + (reg)); 948 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) 951 uint32_t reg, uint32_t val) 954 iowrite16((val), dev_priv->vdc_reg + (reg)); 957 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) 960 uint32_t reg, uint32_t val) 963 iowrite8((val), dev_pri 941 REGISTER_WRITE(struct drm_device *dev, uint32_t reg, uint32_t val) argument 950 REGISTER_WRITE16(struct drm_device *dev, uint32_t reg, uint32_t val) argument 959 REGISTER_WRITE8(struct drm_device *dev, uint32_t reg, uint32_t val) argument [all...] |
H A D | psb_intel_sdvo.c | 225 static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val) argument 228 u32 bval = val, cval = val; 711 static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val) argument 713 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 1699 uint64_t val) 1708 ret = drm_connector_property_set_value(connector, property, val); 1713 int i = val; 1734 if (val == !!psb_intel_sdvo->color_range) 1737 psb_intel_sdvo->color_range = val 1697 psb_intel_sdvo_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t val) argument [all...] |
H A D | tc35876x-dsi-lvds.c | 38 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 244 dev_err(&client->dev, "%s: reg 0x%04x val 0x%08x error %d\n", 250 dev_err(&client->dev, "%s: reg 0x%04x val 0x%08x msgs %d\n", 255 dev_dbg(&client->dev, "%s: reg 0x%04x val 0x%08x\n",
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/drivers/gpu/drm/i2c/ |
H A D | ch7006_drv.c | 282 uint64_t val) 294 priv->select_subconnector = val; 301 priv->hmargin = val; 309 priv->vmargin = val; 320 priv->norm = val; 325 priv->brightness = val; 332 priv->contrast = val; 339 priv->flicker = val; 349 priv->scale = val; 395 uint8_t val; local 279 ch7006_encoder_set_property(struct drm_encoder *encoder, struct drm_connector *connector, struct drm_property *property, uint64_t val) argument [all...] |