Searched refs:val (Results 226 - 250 of 2595) sorted by path

1234567891011>>

/drivers/gpio/
H A Dgpio-tps65912.c32 int val; local
34 val = tps65912_reg_read(tps65912, TPS65912_GPIO1 + offset);
36 if (val & GPIO_STS_MASK)
H A Dgpio-ucb1400.c25 static int ucb1400_gpio_dir_out(struct gpio_chip *gc, unsigned off, int val) argument
30 ucb1400_gpio_set_value(gpio->ac97, off, val);
41 static void ucb1400_gpio_set(struct gpio_chip *gc, unsigned off, int val) argument
45 ucb1400_gpio_set_value(gpio->ac97, off, val);
H A Dgpio-vx855.c149 int val)
162 if (val)
167 if (val)
177 unsigned int nr, int val)
186 vx855gpio_set(gpio, nr, val);
148 vx855gpio_set(struct gpio_chip *gpio, unsigned int nr, int val) argument
176 vx855gpio_direction_output(struct gpio_chip *gpio, unsigned int nr, int val) argument
H A Dgpio-wm831x.c42 int val = WM831X_GPN_DIR; local
45 val |= WM831X_GPN_TRI;
49 WM831X_GPN_FN_MASK, val);
82 int val = 0; local
86 val |= WM831X_GPN_TRI;
90 WM831X_GPN_FN_MASK, val);
H A Dgpio-xilinx.c55 * @val: Value to be written to specified signal.
60 static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) argument
70 if (val)
110 * @val: Value to be written to specified signal.
116 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) argument
126 if (val)
/drivers/gpu/drm/
H A Dati_pcigart.c166 u32 val; local
170 val = page_base | 0xc;
173 val = (page_base >> 8) | 0xc;
177 val = page_base;
182 pci_gart[gart_idx] = cpu_to_le32(val);
184 DRM_WRITE32(map, gart_idx * sizeof(u32), val);
H A Ddrm_crtc.c43 char *fnname(int val) \
47 if (list[i].type == val) \
2819 struct drm_property *property, uint64_t *val)
2825 *val = connector->property_values[i];
2818 drm_connector_property_get_value(struct drm_connector *connector, struct drm_property *property, uint64_t *val) argument
/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimd.c198 u32 val; local
209 val = VIDTCON0_VBPD(timing->upper_margin - 1) |
212 writel(val, ctx->regs + VIDTCON0);
215 val = VIDTCON1_HBPD(timing->left_margin - 1) |
218 writel(val, ctx->regs + VIDTCON1);
221 val = VIDTCON2_LINEVAL(timing->yres - 1) |
223 writel(val, ctx->regs + VIDTCON2);
226 val = ctx->vidcon0;
227 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
230 val |
245 u32 val; local
272 u32 val; local
354 unsigned long val; local
432 unsigned long val, alpha, size; local
543 u32 val; local
639 u32 val; local
734 u32 val; local
[all...]
H A Dexynos_hdmi.c1197 u32 val = hdmi_reg_read(hdata, HDMI_HPD_STATUS); local
1199 if (val)
1384 u32 val; local
1426 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1427 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1609 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS); local
1610 if (val & HDMI_PHY_STATUS_READY)
1776 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0); local
1777 if (val & HDMI_PHY_STATUS_READY)
H A Dexynos_mixer.c122 u32 val)
124 writel(val, res->vp_regs + reg_id);
128 u32 val, u32 mask)
132 val = (val & mask) | (old & ~mask);
133 writel(val, res->vp_regs + reg_id);
142 u32 val)
144 writel(val, res->mixer_regs + reg_id);
148 u32 reg_id, u32 val, u32 mask)
152 val
121 vp_reg_write(struct mixer_resources *res, u32 reg_id, u32 val) argument
127 vp_reg_writemask(struct mixer_resources *res, u32 reg_id, u32 val, u32 mask) argument
141 mixer_reg_write(struct mixer_resources *res, u32 reg_id, u32 val) argument
147 mixer_reg_writemask(struct mixer_resources *res, u32 reg_id, u32 val, u32 mask) argument
229 u32 val = (data[0] << 24) | (data[1] << 16) | local
260 u32 val; local
284 u32 val; local
325 u32 val = enable ? ~0 : 0; local
363 u32 val; local
493 u32 val; local
776 u32 val, val_base; local
818 u32 val; /* value stored to register */ local
[all...]
H A Dregs-mixer.h68 #define MXR_MASK_VAL(val, high_bit, low_bit) \
69 (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit))
H A Dregs-vp.h58 #define VP_MASK_VAL(val, high_bit, low_bit) \
59 (((val) << (low_bit)) & VP_MASK(high_bit, low_bit))
/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c135 static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) argument
157 *val = REG_READ(SB_DATA);
162 static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) argument
171 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
181 REG_WRITE(SB_DATA, val);
H A Dintel_gmbus.c83 u32 val;
88 val = REG_READ(DSPCLK_GATE_D);
90 val |= DPCUNIT_CLOCK_GATE_DISABLE;
92 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
93 REG_WRITE(DSPCLK_GATE_D, val);
278 u32 val, loop = 0; local
285 val = REG_READ(GMBUS3 + reg_offset);
287 *buf++ = val & 0xff;
288 val >>= 8;
292 u32 val, loo local
[all...]
H A Dintel_i2c.c37 u32 val; local
39 val = REG_READ(chan->reg);
40 return (val & GPIO_CLOCK_VAL_IN) != 0;
47 u32 val; local
49 val = REG_READ(chan->reg);
50 return (val & GPIO_DATA_VAL_IN) != 0;
H A Dmdfld_dsi_dpi.c473 u32 val; local
485 val = lane_count;
486 val |= dsi_config->channel_num << DSI_DPI_VIRT_CHANNEL_OFFSET;
490 val |= DSI_DPI_COLOR_FORMAT_RGB565;
493 val |= DSI_DPI_COLOR_FORMAT_RGB666;
496 val |= DSI_DPI_COLOR_FORMAT_RGB888;
502 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val); local
546 val = dsi_config->video_mode | DSI_DPI_COMPLETE_LAST_LINE;
547 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val); local
H A Dmdfld_dsi_output.c252 uint64_t val; local
268 if (drm_connector_property_get_value(connector, property, &val))
271 if (val == value)
278 centerechange = (val == DRM_MODE_SCALE_NO_SCALE) ||
H A Dmdfld_dsi_output.h45 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
46 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
47 #define FLD_MOD(orig, val, start, end) \
48 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
50 #define REG_FLD_MOD(reg, val, start, end) \
51 REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))
54 u32 val, int start, int end)
58 while (FLD_GET(REG_READ(reg), start, end) != val) {
53 REGISTER_FLD_WAIT(struct drm_device *dev, u32 reg, u32 val, int start, int end) argument
[all...]
H A Dmdfld_dsi_pkg_sender.c233 u32 val; local
246 val = FLD_VAL(param, 23, 16) | FLD_VAL(cmd, 15, 8) |
249 REG_WRITE(ctrl_reg, val);
260 u32 val; local
310 val = FLD_VAL(len, 23, 8) | FLD_VAL(virtual_channel, 7, 6) |
313 REG_WRITE(ctrl_reg, val);
H A Doaktrail_hdmi.c34 #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
H A Doaktrail_hdmi_i2c.c36 #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
265 DRM_DEBUG_DRIVER("old gpio val %x\n", temp);
268 DRM_DEBUG_DRIVER("new gpio val %x\n", temp);
H A Dpsb_drv.h942 uint32_t val)
945 iowrite32((val), dev_priv->vdc_reg + (reg));
948 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
951 uint32_t reg, uint32_t val)
954 iowrite16((val), dev_priv->vdc_reg + (reg));
957 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
960 uint32_t reg, uint32_t val)
963 iowrite8((val), dev_pri
941 REGISTER_WRITE(struct drm_device *dev, uint32_t reg, uint32_t val) argument
950 REGISTER_WRITE16(struct drm_device *dev, uint32_t reg, uint32_t val) argument
959 REGISTER_WRITE8(struct drm_device *dev, uint32_t reg, uint32_t val) argument
[all...]
H A Dpsb_intel_sdvo.c225 static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val) argument
228 u32 bval = val, cval = val;
711 static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val) argument
713 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
1699 uint64_t val)
1708 ret = drm_connector_property_set_value(connector, property, val);
1713 int i = val;
1734 if (val == !!psb_intel_sdvo->color_range)
1737 psb_intel_sdvo->color_range = val
1697 psb_intel_sdvo_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t val) argument
[all...]
H A Dtc35876x-dsi-lvds.c38 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
244 dev_err(&client->dev, "%s: reg 0x%04x val 0x%08x error %d\n",
250 dev_err(&client->dev, "%s: reg 0x%04x val 0x%08x msgs %d\n",
255 dev_dbg(&client->dev, "%s: reg 0x%04x val 0x%08x\n",
/drivers/gpu/drm/i2c/
H A Dch7006_drv.c282 uint64_t val)
294 priv->select_subconnector = val;
301 priv->hmargin = val;
309 priv->vmargin = val;
320 priv->norm = val;
325 priv->brightness = val;
332 priv->contrast = val;
339 priv->flicker = val;
349 priv->scale = val;
395 uint8_t val; local
279 ch7006_encoder_set_property(struct drm_encoder *encoder, struct drm_connector *connector, struct drm_property *property, uint64_t val) argument
[all...]

Completed in 221 milliseconds

1234567891011>>