Searched refs:DPRINT (Results 1 - 6 of 6) sorted by relevance

/arch/ia64/kernel/
H A Dperfmon.c162 DPRINT(("spinlock_irq_save ctx %p by [%d]\n", c, task_pid_nr(current))); \
164 DPRINT(("spinlocked ctx %p by [%d]\n", c, task_pid_nr(current))); \
169 DPRINT(("spinlock_irq_restore ctx %p by [%d]\n", c, task_pid_nr(current))); \
229 #define DPRINT(a) \ macro
779 DPRINT(("ctx_fd=%p head=%d tail=%d\n", ctx, ctx->ctx_msgq_head, ctx->ctx_msgq_tail));
785 DPRINT(("ctx=%p head=%d tail=%d msg=%d\n", ctx, ctx->ctx_msgq_head, ctx->ctx_msgq_tail, idx));
795 DPRINT(("ctx=%p head=%d tail=%d\n", ctx, ctx->ctx_msgq_head, ctx->ctx_msgq_tail));
809 DPRINT(("ctx=%p head=%d tail=%d type=%d\n", ctx, ctx->ctx_msgq_head, ctx->ctx_msgq_tail, msg->pfm_gen_msg.msg_type));
818 DPRINT(("ctx=%p msgq reset\n", ctx));
847 DPRINT(("freein
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H A Dunaligned.c33 # define DPRINT(a...) do { printk("%s %u: ", __func__, __LINE__); printk (a); } while (0) macro
48 # define DPRINT(a...) macro
319 DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
326 DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",
347 DPRINT("ignoring kernel write to r%lu; register isn't on the kernel RBS!", r1);
356 DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);
363 DPRINT("rnat @%p = 0x%lx nat=%d old nat=%ld\n",
373 DPRINT("rnat changed to @%p = 0x%lx\n", (void *) rnat_addr, rnats);
392 DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
399 DPRINT("
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H A Dperfmon_default_smpl.c25 #define DPRINT(a) \ macro
36 #define DPRINT(a) macro
47 DPRINT(("[%d] no argument passed\n", task_pid_nr(task)));
51 DPRINT(("[%d] validate flags=0x%x CPU%d\n", task_pid_nr(task), flags, cpu));
58 DPRINT(("buf_size=%lu\n", arg->buf_size));
90 DPRINT(("[%d] buffer=%p buf_size=%lu hdr_size=%lu hdr_version=%u cur_offs=%lu\n",
113 DPRINT(("[%d] invalid arguments buf=%p arg=%p\n", task->pid, buf, arg));
248 DPRINT(("[%d] exit(%p)\n", task_pid_nr(task), buf));
H A Dperfmon_montecito.h146 DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n",
185 DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, tmpval, ctx->ctx_fl_using_dbreg, is_loaded));
190 DPRINT(("pmc[%d]=0x%lx has active pmc41 settings, clearing dbr\n", cnum, tmpval));
210 DPRINT(("pmc38=0x%lx has active pmc38 settings, clearing ibr\n", tmpval));
248 DPRINT(("invalid config pmc38=0x%lx pmc41=0x%lx pmc32=0x%lx\n", val38, val41, val32));
H A Dperfmon_mckinley.h68 DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n",
101 DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, *val, ctx->ctx_fl_using_dbreg, is_loaded));
106 DPRINT(("pmc[%d]=0x%lx has active pmc13 settings, clearing dbr\n", cnum, *val));
124 DPRINT(("pmc[%d]=0x%lx has active pmc14 settings, clearing ibr\n", cnum, *val));
166 if (ret) DPRINT((KERN_DEBUG "perfmon: failure check_case1\n"));
H A Dperfmon_itanium.h67 DPRINT(("pmc[%d]=0x%lx has active pmc13.ta cleared, clearing ibr\n", cnum, *val));
86 DPRINT(("pmc[%d]=0x%lx has active pmc11.pt cleared, clearing dbr\n", cnum, *val));

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