Searched refs:MSC1 (Results 1 - 8 of 8) sorted by relevance

/arch/arm/mach-pxa/
H A Dsmemc.c22 msc[1] = __raw_readl(MSC1);
36 __raw_writel(msc[1], MSC1);
H A Dxcep.c173 __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1);
H A Dh5000.c178 __raw_writel(0x7ff424fa, MSC1);
H A Dcm-x2xx.c398 sleep_save_msc[1] = __raw_readl(MSC1);
422 __raw_writel(sleep_save_msc[1], MSC1);
H A Dzeus.c835 msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
837 __raw_writel(msc1, MSC1);
/arch/arm/mach-pxa/include/mach/
H A Dsmemc.h21 #define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */ macro
/arch/arm/mach-sa1100/
H A Dsleep.S66 * r1 = &MSC1
69 * r4 = MSC1 value
82 ldr r1, =MSC1
/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1468 * MSC1 Memory system: Static memory Control register 1
1477 #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */ macro

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