Searched refs:UART_LCR (Results 1 - 15 of 15) sorted by relevance

/arch/frv/kernel/
H A Dgdb-io.h24 #undef UART_LCR macro
37 #define UART_LCR 3*8 /* Out: Line Control Register */ macro
/arch/powerpc/boot/
H A Dvirtex.c21 #define UART_LCR 3 /* Out: Line Control Register */ macro
58 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB);
65 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8);
H A Dns16550.c21 #define UART_LCR 3 /* Out: Line Control Register */ macro
/arch/powerpc/platforms/embedded6xx/
H A Dls_uart.c66 out_8(avr_addr + UART_LCR, cval); /* initialise UART */
72 out_8(avr_addr + UART_LCR, cval); /* Set character format */
74 out_8(avr_addr + UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
77 out_8(avr_addr + UART_LCR, cval); /* reset DLAB */
/arch/arm/mach-tegra/include/mach/
H A Duncompress.h152 uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB;
155 uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
/arch/mips/pmc-sierra/msp71xx/
H A Dmsp_serial.c50 if (offset == UART_LCR)
83 writeb(d->last_lcr, p->membase + (UART_LCR << p->regshift));
/arch/x86/platform/mrst/
H A Dearly_printk_mrst.c271 lcr = readb(phsu + UART_LCR);
272 writeb((0x80 | lcr), phsu + UART_LCR);
274 writeb(lcr, phsu + UART_LCR);
279 writeb(0x3, phsu + UART_LCR);
/arch/mn10300/unit-asb2303/include/unit/
H A Dserial.h72 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
87 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LCR * 4, u8)
/arch/mips/cavium-octeon/
H A Dserial.c41 if (offset == UART_LCR)
/arch/mn10300/unit-asb2305/include/unit/
H A Dserial.h63 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
/arch/mn10300/unit-asb2364/include/unit/
H A Dserial.h69 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 2, u8)
/arch/sh/include/asm/
H A Dsmc37c93x.h61 #define UART_LCR 0x6 /* Line Control Register */ macro
/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h496 #define bfin_read_UART_LCR() bfin_read16(UART_LCR)
497 #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
/arch/mips/include/asm/mach-au1x00/
H A Dau1000.h1167 #define UART_LCR 0x14 /* Line Control Register */ macro
/arch/blackfin/mach-bf561/include/mach/
H A DcdefBF561.h125 #define bfin_read_UART_LCR() bfin_read16(UART_LCR)
126 #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)

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