Searched refs:XCHAL_DCACHE_LINEWIDTH (Results 1 - 5 of 5) sorted by relevance

/arch/xtensa/include/asm/
H A Dcache.h16 #define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
22 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
H A Dcacheasm.h76 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
93 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
100 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
108 XCHAL_DCACHE_LINEWIDTH
124 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
131 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
138 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
153 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
160 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
167 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
[all...]
/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h117 #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ macro
/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h124 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/arch/xtensa/variants/s6000/include/variant/
H A Dcore.h123 #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ macro

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