Searched refs:a3 (Results 1 - 25 of 107) sorted by relevance

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/arch/xtensa/kernel/
H A Dcoprocessor.S35 * a3: dispatch table
37 * excsave_1: a3
130 * a2 a3
132 * a2 a3
145 addx8 a3, a3, a0
146 l32i a3, a3, 0
147 beqz a3, 1f
148 add a0, a0, a3
[all...]
H A Dvectors.S31 * a3: dispatch table
33 * excsave_1: a3
72 xsr a3, EXCSAVE_1 # save a3 and get dispatch table
74 l32i a2, a3, EXC_TABLE_KSTK # load kernel stack to a2
78 addx4 a0, a0, a3 # find entry in table
96 xsr a3, EXCSAVE_1 # save a3, and get dispatch table
102 addx4 a0, a0, a3 # find entry in table
152 * - The handler can use any other generic register from a3 t
[all...]
H A Dentry.S95 * a3: dispatch table
97 * excsave1: a3
104 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
113 /* Save a2, a3, and depc, restore excsave_1 and set SP. */
115 xsr a3, EXCSAVE_1
119 s32i a3, a2, PT_AREG3
128 rsr a3, SAR
130 s32i a3, a1, PT_SAR
137 rsr a3, WINDOWSTART
140 s32i a3, a
[all...]
H A Dalign.S149 * a3: dispatch table
151 * excsave_1: a3
174 xsr a3, EXCSAVE_1
176 s32i a3, a2, PT_AREG3
196 /* a3...a6 saved on stack, a2 = SP */
201 movi a3, ~3
202 and a3, a3, a7 # mask lower bits
204 l32i a4, a3, 0 # load 2 words
205 l32i a5, a3,
[all...]
H A Dhead.S139 * a2, a3 are just working registers (clobbered).
143 ___unlock_dcache_all a2 a3
147 ___unlock_icache_all a2 a3
150 ___invalidate_dcache_all a2 a3
151 ___invalidate_icache_all a2 a3
165 movi a3, __boot_reloc_table_end
167 1: beq a2, a3, 3f # no more entries?
188 movi a3, __bss_stop # end of BSS
190 __loopt a2, a3, a4, 2
200 ___flush_dcache_all a2 a3
[all...]
/arch/xtensa/mm/
H A Dmisc.S34 movi a3, 0
36 s32i a3, a2, 0
37 s32i a3, a2, 4
38 s32i a3, a2, 8
39 s32i a3, a2, 12
40 s32i a3, a2, 16
41 s32i a3, a2, 20
42 s32i a3, a2, 24
43 s32i a3, a2, 28
52 * a2 a3
[all...]
/arch/xtensa/lib/
H A Dmemcopy.S67 * a3/ src
84 # a2=src, a3=dst, a4=len
85 mov a5, a3 # copy dst so that a2 is return value
86 mov a3, a2
102 add a7, a3, a4 # a7 = end address for source
105 l8ui a6, a3, 0
106 addi a3, a3, 1
110 blt a3, a7, .Lnextbyte
124 l8ui a6, a3,
[all...]
H A Dusercopy.S45 * a3/ src
81 # a2/ dst, a3/ src, a4/ len
91 bnone a3, a8, .Laligned # then use word copy
92 SSA8( a3) # set shift amount from byte offset
105 EX(l8ui, a6, a3, 0, l_fixup)
106 addi a3, a3, 1
115 EX(l8ui, a6, a3, 0, l_fixup)
116 EX(l8ui, a7, a3, 1, l_fixup)
117 addi a3, a
[all...]
H A Dchecksum.S29 * a3 = len
53 srli a5, a3, 5 /* 32-byte chunks */
83 extui a5, a3, 2, 3 /* remaining 4-byte chunks */
99 _bbci.l a3, 1, 5f /* remaining 2-byte chunk */
104 _bbci.l a3, 0, 7f /* remaining 1-byte chunk */
116 beqz a3, 7b /* branch if len == 0 */
117 beqi a3, 1, 6b /* branch if len == 1 */
125 addi a3, a3, -2 /* adjust len */
133 srli a5, a3,
303 a3 = dst define
[all...]
H A Dmemset.S46 # a2/ dst, a3/ c, a4/ length
47 extui a3, a3, 0, 8 # mask to just 8 bits
48 slli a7, a3, 8 # duplicate character in all bytes of word
49 or a3, a3, a7 # ...
50 slli a7, a3, 16 # ...
51 or a3, a3, a7 # ...
76 EX(s32i, a3, a
[all...]
H A Dstrncpy_user.S45 # a3/ src
62 # a2/ dst, a3/ src, a4/ len
69 bbsi.l a3, 0, .Lsrc1mod2 # if only 8-bit aligned
70 bbsi.l a3, 1, .Lsrc2mod4 # if only 16-bit aligned
78 EX(l8ui, a9, a3, 0, fixup_l) # get byte 0
79 addi a3, a3, 1 # advance src pointer
85 bbci.l a3, 1, .Lsrcaligned # if src is now word-aligned
88 EX(l8ui, a9, a3, 0, fixup_l) # get byte 0
95 EX(l8ui, a9, a3,
[all...]
/arch/x86/include/asm/
H A Defi.h13 #define efi_call_phys3(f, a1, a2, a3) efi_call_phys(f, a1, a2, a3)
14 #define efi_call_phys4(f, a1, a2, a3, a4) \
15 efi_call_phys(f, a1, a2, a3, a4)
16 #define efi_call_phys5(f, a1, a2, a3, a4, a5) \
17 efi_call_phys(f, a1, a2, a3, a4, a5)
18 #define efi_call_phys6(f, a1, a2, a3, a4, a5, a6) \
19 efi_call_phys(f, a1, a2, a3, a4, a5, a6)
30 #define efi_call_virt3(f, a1, a2, a3) efi_call_virt(f, a1, a2, a3)
[all...]
/arch/mn10300/kernel/
H A Dkernel_execve.S29 mov a3,a1
31 mov (12,sp),a3
34 mov a1,a3
H A Dmn10300-serial-low.S44 movm [d2,d3,a2,a3,exreg0],(sp)
52 mov (a2+),a3
53 mov (__iobase,a3),e2
69 mov (__rx_icr,a3),e3
74 mov (__rx_inp,a3),d3
78 mov (__rx_outp,a3),d2
82 mov (__rx_buffer,a3),d2
88 mov d3,(__rx_inp,a3)
89 bset MNSCx_RX_AVAIL,(__intr_flags,a3)
92 mov (__tm_icr,a3),a
[all...]
H A Dgdb-io-serial-low.S35 movm [d2,d3,a2,a3],(sp)
41 mov (gdbstub_rx_inp),a3
43 mov a3,a2
44 add 2,a3
45 and 0x00000fff,a3
47 cmp a3,d3
56 mov a3,(gdbstub_rx_inp)
63 movm (sp),[d2,d3,a2,a3]
H A Dgdb-io-ttysm-low.S35 movm [d2,d3,a2,a3],(sp)
37 mov (gdbstub_rx_inp),a3
39 mov a3,a2
40 add 2,a3
41 and PAGE_SIZE_asm-1,a3
43 cmp a3,d3
52 mov a3,(gdbstub_rx_inp)
60 movm (sp),[d2,d3,a2,a3]
/arch/xtensa/boot/boot-redboot/
H A Dbootstrap.S31 # a3: Size of parameter list
133 # a3: length of parameter list
139 add a3, a2, a3
145 blt a2, a3, 2b
167 movi a3, __image_load
168 sub a4, a3, a4
230 movi a3, boot_initrd_start
232 sub a3, a3, a
[all...]
/arch/cris/arch-v32/drivers/
H A DMakefile8 obj-$(CONFIG_CRIS_MACH_ARTPEC3) += mach-a3/
/arch/mips/boot/compressed/
H A Dhead.S26 move s3, a3
46 move a3, s3
/arch/alpha/include/asm/
H A Dregdef.h27 #define a3 $19 macro
/arch/mn10300/include/asm/
H A Dsigcontext.h28 unsigned long a3; member in struct:sigcontext
/arch/xtensa/boot/boot-elf/
H A Dbootstrap.S19 movi a3, 0
/arch/arm/include/asm/
H A Dxor.h21 : "=r" (dst), "=r" (a1), "=r" (a2), "=r" (a3), "=r" (a4) \
34 __XOR(a1, b1); __XOR(a2, b2); __XOR(a3, b3); __XOR(a4, b4)
44 : "0" (dst), "r" (a1), "r" (a2), "r" (a3), "r" (a4))
52 register unsigned int a3 __asm__("r6");
73 register unsigned int a3 __asm__("r6");
/arch/x86/platform/uv/
H A Dbios_uv.c31 s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5) argument
43 a1, a2, a3, a4, a5);
48 s64 uv_bios_call_irqsave(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, argument
55 ret = uv_bios_call(which, a1, a2, a3, a4, a5);
61 s64 uv_bios_call_reentrant(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, argument
67 ret = uv_bios_call(which, a1, a2, a3, a4, a5);
/arch/m68k/lib/
H A Dmulsi3.S83 #define a3 REG (a3) define

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