Searched refs:bit (Results 1 - 25 of 388) sorted by relevance

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/arch/sh/boards/mach-x3proto/
H A Dilsel.c40 * 1:1 mapping between the bit position and the IRQ number.
49 static inline unsigned int ilsel_offset(unsigned int bit) argument
51 return ILSEL_LEVELS - bit - 1;
54 static inline unsigned long mk_ilsel_addr(unsigned int bit) argument
56 return ILSEL_BASE + ((ilsel_offset(bit) >> 1) & ~0x1);
59 static inline unsigned int mk_ilsel_shift(unsigned int bit) argument
61 return (ilsel_offset(bit) & 0x3) << 2;
64 static void __ilsel_enable(ilsel_source_t set, unsigned int bit) argument
71 addr = mk_ilsel_addr(bit);
72 shift = mk_ilsel_shift(bit);
97 unsigned int bit; local
127 unsigned int bit = ilsel_offset(level - 1); local
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/arch/s390/include/asm/
H A Dctl_reg.h48 #define __ctl_set_bit(cr, bit) ({ \
51 __dummy |= 1UL << (bit); \
55 #define __ctl_clear_bit(cr, bit) ({ \
58 __dummy &= ~(1UL << (bit)); \
64 extern void smp_ctl_set_bit(int cr, int bit);
65 extern void smp_ctl_clear_bit(int cr, int bit);
66 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
67 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
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/arch/x86/include/asm/
H A Dcpufeature.h9 #define NCAPINTS 10 /* N 32-bit words worth of info */
14 * this feature bit is not displayed in /proc/cpuinfo at all.
35 #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
104 #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
129 #define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */
150 #define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */
151 #define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
164 #define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
202 #define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */
206 #define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulatio
342 __static_cpu_has(u16 bit) argument
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/arch/m68k/math-emu/
H A Dfp_emu.h52 #define fp_set_sr(bit) ({ \
53 FPDATA->fpsr |= 1 << (bit); \
130 * set, reset or clear a bit in the fp status register
132 .macro fp_set_sr bit
133 bset #(\bit&7),(FPD_FPSR+3-(\bit/8),FPDATA)
136 .macro fp_clr_sr bit
137 bclr #(\bit&7),(FPD_FPSR+3-(\bit/8),FPDATA)
140 .macro fp_tst_sr bit
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/arch/alpha/kernel/
H A Dsys_sable.c39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
93 sable_update_irq_hw(unsigned long bit, unsigned long mask) argument
97 if (bit >= 16) {
100 } else if (bit >= 8) {
109 sable_ack_irq_hw(unsigned long bit) argument
113 if (bit >= 16) {
115 val1 = 0xE0 | (bit - 16);
117 } else if (bit >
292 lynx_update_irq_hw(unsigned long bit, unsigned long mask) argument
308 lynx_ack_irq_hw(unsigned long bit) argument
447 unsigned long bit, mask; local
463 unsigned long bit, mask; local
479 unsigned long bit, mask; local
503 int bit, irq; local
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/arch/arm/mach-pnx4008/
H A Dgpio.c54 u32 bit, val; local
60 bit = GPIO_BIT(gpio);
61 if (bit) {
63 ret = (val & bit) ? 1 : 0;
71 u32 bit, val; local
77 bit = GPIO_BIT(gpio);
78 if (bit) {
80 val |= bit;
121 unsigned long bit = GPIO_BIT(pin); local
127 if (access_map[GPIO_INDEX] & bit)
163 unsigned long bit = GPIO_BIT(pin); local
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/arch/mips/include/asm/
H A Dbitops.h49 * set_bit - Atomically set a bit in memory
50 * @nr: the bit to set
61 unsigned short bit = nr & SZLONG_MASK; local
73 : "ir" (1UL << bit), "m" (*m));
75 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
82 : "ir" (bit), "r" (~0));
94 : "ir" (1UL << bit));
102 mask = 1UL << bit;
110 * clear_bit - Clears a bit in memory
122 unsigned short bit local
195 unsigned short bit = nr & SZLONG_MASK; local
248 unsigned short bit = nr & SZLONG_MASK; local
314 unsigned short bit = nr & SZLONG_MASK; local
377 unsigned short bit = nr & SZLONG_MASK; local
461 unsigned short bit = nr & SZLONG_MASK; local
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/arch/arm/plat-samsung/include/plat/
H A Dwakeup-mask.h22 * @bit: The bit, as a (1 << bitno) controlling this source.
26 u32 bit; member in struct:samsung_wakeup_mask
H A Dirq.h72 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); local
76 __raw_writel(bit, S3C2410_SUBSRCPND);
93 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); local
95 __raw_writel(bit, S3C2410_SUBSRCPND);
/arch/h8300/include/asm/
H A Dgpio-internal.h40 #define H8300_GPIO_DDR(port, bit, dir) \
41 h8300_set_gpio_dir(((port) << 8) | (bit), dir)
43 #define H8300_GPIO_GETDIR(port, bit) \
44 h8300_get_gpio_dir(((port) << 8) | (bit))
/arch/mips/loongson/common/
H A Dmem.c26 int bit; local
28 bit = fls(memsize + highmemsize);
29 if (bit != ffs(memsize + highmemsize))
30 bit += 20;
32 bit = bit + 20 - 1;
36 0x80000000ul, (1 << bit));
/arch/mips/include/asm/mach-au1x00/
H A Dgpio-au1300.h31 int bit; local
35 bit = GPIC_GPIO_TO_BIT(gpio);
36 return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
42 unsigned long bit; local
47 bit = GPIC_GPIO_TO_BIT(gpio);
48 __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
57 unsigned long bit; local
62 bit = GPIC_GPIO_TO_BIT(gpio);
63 __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
/arch/arm/plat-samsung/
H A Dwakeup-mask.c32 val |= mask->bit;
38 /* bit of a liberty to read this directly from irq_data. */
40 val &= ~mask->bit;
42 val |= mask->bit;
/arch/powerpc/sysdev/
H A Dcpm2_pic.c19 * There are two 32-bit registers (high/low) for up to 64
24 * That is, interrupt 4 does not map to bit position 4.
26 * which register to use and which bit in the register to use.
54 static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */
67 /* bit numbers do not match the docs, these are precomputed so the bit for
82 int bit, word; local
85 bit = irq_to_siubit[irq_nr];
88 ppc_cached_irq_mask[word] &= ~(1 << bit);
94 int bit, wor local
106 int bit, word; local
117 int bit, word; local
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H A Dipic.c42 .bit = 16,
49 .bit = 17,
56 .bit = 18,
63 .bit = 19,
70 .bit = 20,
77 .bit = 21,
84 .bit = 22,
91 .bit = 23,
98 .bit = 24,
105 .bit
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/arch/mips/alchemy/common/
H A Dirq.c290 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; local
293 __raw_writel(1 << bit, base + IC_MASKSET);
294 __raw_writel(1 << bit, base + IC_WAKESET);
300 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; local
303 __raw_writel(1 << bit, base + IC_MASKSET);
304 __raw_writel(1 << bit, base + IC_WAKESET);
310 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; local
313 __raw_writel(1 << bit, base + IC_MASKCLR);
314 __raw_writel(1 << bit, base + IC_WAKECLR);
320 unsigned int bit local
330 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; local
344 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; local
358 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; local
370 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; local
382 int bit = d->irq - AU1000_INTC1_INT_BASE; local
430 unsigned int bit, irq = d->irq; local
553 unsigned long bit; local
604 unsigned long bit, irq = d->irq; local
618 unsigned long bit, irq = d->irq; local
633 unsigned long bit, irq = d->irq; local
648 unsigned long bit, irq = d->irq; local
879 unsigned int bit, irq_nr; local
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/arch/arm/include/asm/
H A Dbitops.h8 * bit 0 is the LSB of an "unsigned long" quantity.
33 * These functions are the basis of our bit ops.
37 static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p) argument
40 unsigned long mask = 1UL << (bit & 31);
42 p += bit >> 5;
49 static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p) argument
52 unsigned long mask = 1UL << (bit & 31);
54 p += bit >> 5;
61 static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p) argument
64 unsigned long mask = 1UL << (bit
74 ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p) argument
91 ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p) argument
108 ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) argument
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/arch/frv/include/asm/
H A Dbitops.h1 /* bitops.h: bit operations for the Fujitsu FR-V CPUs
247 * fls - find last bit set
251 * - return 32..1 to indicate bit 31..0 most significant bit set
256 int bit; \
263 : "=&r"(bit) \
268 bit; \
272 * fls64 - find last bit set in a 64-bit value
276 * - return 64..1 to indicate bit 6
286 int bit, x, y; local
338 int bit; local
351 unsigned long bit; local
364 int bit; local
381 int bit, x, y; local
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H A Dmath-emu.h108 #define dprint(bit, fmt, args...) ({ \
109 if (fp_debugprint & (1 << (bit))) \
113 #define dprint(bit, fmt, args...)
237 .macro printf bit=-1,string,nr=0,arg1,arg2,arg3,arg4,arg5
245 .if \bit+1
247 moveq #\bit,%d0
249 btst %d0,fp_debugprint+((31-\bit)/8)
251 btst #\bit,fp_debugprint+((31-\bit)/8)
264 .macro printx bit,f
285 printf \\bit," %08x%08x%08x",3,%a0@,%a0@(4),%a0@(8) variable
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/arch/mips/include/asm/mach-ar7/
H A Dar7.h167 static inline void ar7_device_enable(u32 bit) argument
171 writel(readl(reset_reg) | (1 << bit), reset_reg);
175 static inline void ar7_device_disable(u32 bit) argument
179 writel(readl(reset_reg) & ~(1 << bit), reset_reg); local
183 static inline void ar7_device_reset(u32 bit) argument
185 ar7_device_disable(bit);
186 ar7_device_enable(bit);
189 static inline void ar7_device_on(u32 bit) argument
192 writel(readl(power_reg) | (1 << bit), power_reg);
196 static inline void ar7_device_off(u32 bit) argument
199 writel(readl(power_reg) & ~(1 << bit), power_reg); local
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/arch/ia64/include/asm/
H A Dbitops.h21 * set_bit - Atomically set a bit in memory
22 * @nr: the bit to set
35 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
40 __u32 bit, old, new; local
45 bit = 1 << (nr & 31);
49 new = old | bit;
54 * __set_bit - Set a bit in memory
55 * @nr: the bit to set
75 * clear_bit - Clears a bit i
168 __u32 bit, old, new; local
207 __u32 bit, old, new; local
306 __u32 bit, old, new; local
330 __u32 old, bit = (1 << (nr & 31)); local
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/arch/m68k/include/asm/
H A Dmath-emu.h108 #define dprint(bit, fmt, args...) ({ \
109 if (fp_debugprint & (1 << (bit))) \
113 #define dprint(bit, fmt, args...)
252 .macro printf bit=-1,string,nr=0,arg1,arg2,arg3,arg4,arg5
260 .if \bit+1
262 moveq #\bit,%d0
264 btst %d0,fp_debugprint+((31-\bit)/8)
266 btst #\bit,fp_debugprint+((31-\bit)/8)
279 .macro printx bit,f
300 printf \\bit," %08x%08x%08x",3,%a0@,%a0@(4),%a0@(8) variable
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/arch/mips/txx9/jmr3927/
H A Dirq.c55 unsigned int bit = 1 << irq_nr; local
56 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
65 unsigned int bit = 1 << irq_nr; local
66 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
/arch/sh/boards/mach-se/7343/
H A Dirq.c23 unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data); local
24 __raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
29 unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data); local
30 __raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
/arch/sh/boards/mach-se/7722/
H A Dirq.c23 unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data); local
24 __raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
29 unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data); local
30 __raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);

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