/arch/arm/mach-rpc/include/mach/ |
H A D | acornfb.h | 98 case 1: vidc->control |= VIDC20_CTRL_PIX_CK; break; 99 case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break; 100 case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break; 101 case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break; 102 case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break; 103 case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break; 104 case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break; 105 case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break; 118 vidc->control |= VIDC20_CTRL_FIFO_24; 120 vidc->control | [all...] |
/arch/powerpc/boot/ |
H A D | mv64x60_i2c.c | 75 static int mv64x60_i2c_control(int control, int status) argument 77 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); 81 static int mv64x60_i2c_read_byte(int control, int status) argument 83 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); 89 static int mv64x60_i2c_write_byte(int data, int control, int status) argument 92 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); 101 int control; local 118 control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; 120 if (mv64x60_i2c_control(control, status) < 0) 125 control [all...] |
/arch/arm/boot/compressed/ |
H A D | big-endian.S | 10 mrc p15, 0, r0, c1, c0, 0 @ read control reg 12 mcr p15, 0, r0, c1, c0, 0 @ write control reg
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/arch/um/drivers/ |
H A D | daemon.h | 20 int control; member in struct:daemon_data
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H A D | daemon_user.c | 55 pri->control = socket(AF_UNIX, SOCK_STREAM, 0); 56 if (pri->control < 0) { 58 printk(UM_KERN_ERR "daemon_open : control socket failed, " 63 if (connect(pri->control, (struct sockaddr *) ctl_addr, 66 printk(UM_KERN_ERR "daemon_open : control connect failed, " 97 n = write(pri->control, &req, sizeof(req)); 99 printk(UM_KERN_ERR "daemon_open : control setup request " 105 n = read(pri->control, sun, sizeof(*sun)); 121 close(pri->control); 166 close(pri->control); [all...] |
/arch/mips/oprofile/ |
H A D | op_model_rm9000.c | 32 unsigned int control; member in struct:rm9k_register_config 41 unsigned int control = 0; local 43 /* Compute the performance counter control word. */ 46 control |= RM9K_COUNTER1_EVENT(ctr[0].event) | 51 control |= RM9K_COUNTER2_EVENT(ctr[1].event) | 55 reg.control = control; 74 write_c0_perfcontrol(reg.control); 85 unsigned int control = read_c0_perfcontrol(); local 102 if (control [all...] |
H A D | op_model_mipsxx.c | 128 unsigned int control[4]; member in struct:mipsxx_register_config 139 /* Compute the performance counter control word. */ 141 reg.control[i] = 0; 147 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | 150 reg.control[i] |= M_PERFCTL_KERNEL; 152 reg.control[i] |= M_PERFCTL_USER; 154 reg.control[i] |= M_PERFCTL_EXL; 188 w_c0_perfctrl3(WHAT | reg.control[3]); 190 w_c0_perfctrl2(WHAT | reg.control[2]); 192 w_c0_perfctrl1(WHAT | reg.control[ 218 unsigned int control; local [all...] |
/arch/mips/pci/ |
H A D | ops-mace.c | 45 u32 control = mace->pci.control; local 48 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT; 63 mace->pci.control = control;
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H A D | pci-rc32434.c | 160 rc32434_pci->pcilba[0].control = 162 dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */ 167 rc32434_pci->pcilba[1].control = 169 dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */ 174 rc32434_pci->pcilba[2].control = 176 dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */ 181 rc32434_pci->pcilba[3].control = 184 dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */
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H A D | msi-octeon.c | 51 * programming the MSI control bits [6:4] before calling 62 u16 control; local 76 &control); 84 configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; 87 request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; 170 control &= ~PCI_MSI_FLAGS_QSIZE; 171 control |= request_private_bits << 4; 173 control);
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/arch/blackfin/include/asm/ |
H A D | bfin_ppi.h | 24 __BFP(control); 43 u32 control; member in struct:bfin_eppi_regs
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H A D | bfin_twi.h | 25 __BFP(control);
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/arch/x86/kvm/ |
H A D | svm.c | 226 vmcb->control.clean = 0; 231 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) 237 vmcb->control.clean &= ~(1 << bit); 255 c = &svm->vmcb->control; 256 h = &svm->nested.hsave->control; 277 vmcb->control.intercept_cr |= (1U << bit); 286 vmcb->control.intercept_cr &= ~(1U << bit); 295 return vmcb->control.intercept_cr & (1U << bit); 302 vmcb->control.intercept_dr |= (1U << bit); 311 vmcb->control 1049 struct vmcb_control_area *control = &svm->vmcb->control; local 3330 struct vmcb_control_area *control = &svm->vmcb->control; local 3434 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; local 3539 struct vmcb_control_area *control; local 3771 struct vmcb_control_area *control = &svm->vmcb->control; local [all...] |
/arch/powerpc/include/asm/ |
H A D | dbdma.h | 12 * DBDMA control/status registers. All little-endian. 15 unsigned int control; /* lets you change bits in status */ member in struct:dbdma_regs 31 /* Bits in control and status registers */ 65 #define KEY_STREAM1 0x100 /* control/status stream */ 72 /* Interrupt control values in command field */ 78 /* Branch control values in command field */ 84 /* Wait control values in command field */ 96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \ 102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
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/arch/sparc/kernel/ |
H A D | psycho_common.c | 37 u64 control; local 57 control = upa_readq(strbuf->strbuf_control); 58 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); 74 upa_writeq(control, strbuf->strbuf_control); 205 u64 control, iommu_tag[16], iommu_data[16]; local 210 control = upa_readq(iommu->iommu_control); 211 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) { 214 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR; 215 upa_writeq(control, iommu->iommu_control); 217 switch ((control 403 u64 control; local [all...] |
H A D | pci_schizo.c | 37 /* Streaming buffer control register. */ 44 /* IOMMU control register. */ 132 u64 control; local 150 control = upa_readq(strbuf->strbuf_control); 151 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB), 168 upa_writeq(control, strbuf->strbuf_control); 241 u64 control; local 245 control = upa_readq(iommu->iommu_control); 246 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { 251 control 1092 u64 control; local 1140 u64 control; local [all...] |
H A D | sbus.c | 34 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */ 497 u64 control; local 532 control = upa_readq(iommu->write_complete_reg); 533 control |= 0x100UL; /* SBUS Error Interrupt Enable */ 534 upa_writeq(control, iommu->write_complete_reg); 546 u64 control; local 551 "control registers.\n"); 588 /* The SYSIO SBUS control register is used for dummy reads 601 control = upa_readq(iommu->iommu_control); 602 control [all...] |
/arch/mips/include/asm/ |
H A D | m48t37.h | 21 volatile u8 control; member in struct:m48t37_rtc
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/arch/arm/mach-ixp4xx/include/mach/ |
H A D | ixp46x_ts.h | 39 u32 control; /* 0x00 Time Sync Control Register */ member in struct:ixp46x_ts_regs
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/arch/mips/include/asm/mach-rc32434/ |
H A D | dma.h | 23 u32 control; /* Control. use DMAD_* */ member in struct:dma_desc 25 u32 devcs; /* Device control and status. */
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/arch/mips/pmc-sierra/yosemite/ |
H A D | setup.c | 80 m48t37_base->control = 0x40; 92 m48t37_base->control = 0x00; 114 m48t37_base->control = 0x80; 135 m48t37_base->control = 0x00;
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/arch/arm/mm/ |
H A D | proc-v6.S | 141 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register 142 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control 143 mrc p15, 0, r9, c1, c0, 0 @ control register 162 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register 163 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control 164 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 166 mov r0, r9 @ control register 181 * on. Return in r0 the new CP15 C1 control register setting. 184 * Harvard cache control instructions insead of the unified cache 185 * control instruction [all...] |
/arch/avr32/mach-at32ap/ |
H A D | at32ap700x.c | 115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control) argument 119 div = PM_BFEXT(PLLDIV, control) + 1; 120 mul = PM_BFEXT(PLLMUL, control) + 1; 196 u32 control; local 198 control = pm_readl(PLL0); 200 return pll_get_rate(clk, control); 240 u32 control; local 242 control = pm_readl(PLL1); 244 return pll_get_rate(clk, control); 371 u32 control; local 515 u32 control; local 527 u32 control; local 539 u32 control; local 565 u32 control; local 592 u32 control; local [all...] |
/arch/tile/kernel/ |
H A D | single_step.c | 398 /* two wide, check for control flow */ 730 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K); local 736 (!(control & SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK))) { 739 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK; 740 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK; 741 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control); 747 * Called from need_singlestep. Set up the control registers and the enable 754 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K); local 757 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK; 758 control | [all...] |
/arch/mips/include/asm/ip32/ |
H A D | mace.h | 49 volatile unsigned int control; member in struct:mace_pci 135 volatile unsigned long control; member in struct:mace_audio 136 volatile unsigned long codec_control; /* codec status control */ 140 volatile unsigned long control; /* channel control */ member in struct:mace_audio::__anon2018 240 volatile unsigned long control; member in struct:mace_ps2port 259 volatile unsigned long control; member in struct:mace_i2c
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