/arch/alpha/lib/ |
H A D | ev6-csum_ipv6_magic.S | 35 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence) 114 cmpult $20,$3,$3 # E : (1 cycle stall on $20) 115 addq $20,$18,$20 # E : U L U L (1 cycle stall on $20) 118 addq $20,$19,$20 # E : (1 cycle stall on $20) 123 addq $18,$19,$18 # E : (1 cycle stall on $19) 126 /* (1 cycle stall on $18, 2 cycles on $20) */ 129 zapnot $0,15,$1 # U : Start folding output (1 cycle stall on $0) 131 srl $0,32,$0 # U : U L U L : (1 cycle stall on $0) 134 extwl $1,2,$2 # U : ushort[1] (1 cycle stall on $1) 135 zapnot $1,3,$0 # U : ushort[0] (1 cycle stal [all...] |
H A D | ev6-memchr.S | 66 extqh $6, $16, $6 # U : 2 cycle stall for $6 106 cmoveq $1, $3, $0 # E : Latency 2, extra map cycle 109 addq $0, 2, $3 # E : U L U L : 2 cycle stall on $0 111 cmoveq $1, $3, $0 # E : Latency 2, extra map cycle 114 addq $0, 1, $3 # E : U L U L : 2 cycle stall on $0 116 cmoveq $1, $3, $0 # E : Latency 2, extra map cycle
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H A D | ev6-memset.S | 151 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle 171 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle 328 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle 348 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle 515 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle 535 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
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H A D | ev6-stxcpy.S | 80 cmpbge zero, t1, t8 # E : (3 cycle stall) 252 zap t0, t8, t0 # U : kill dest bytes <= null (2 cycle data stall)
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H A D | ev6-clear_user.S | 132 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle 170 cmovlt $5, $6, $3 # E : U L L U : Latency 2, extra mapping cycle
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H A D | ev6-copy_user.S | 67 beq $3, $destaligned # .. U .. .. : 2nd (one cycle fetcher stall) 70 * The fetcher stall also hides the 1 cycle cross-cluster stall for $3 (L --> U)
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H A D | ev6-stxncpy.S | 199 extqh t2, a1, t4 # U : (3 cycle stall on t2) 259 extqh t2, a1, t0 # U : extract low bits (2 cycle stall)
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/arch/avr32/mach-at32ap/ |
H A D | hsmc.c | 36 int cycle; local 92 /* Extend read cycle in needed */ 98 cycle = config->ncs_read_setup + config->ncs_read_pulse + recover; 100 if (config->read_cycle < cycle) 101 config->read_cycle = cycle; 103 /* Extend read cycle in needed */ 109 cycle = config->nrd_setup + config->nrd_pulse + recover; 111 if (config->read_cycle < cycle) 112 config->read_cycle = cycle; 114 /* Extend write cycle i 141 u32 setup, pulse, cycle, mode; local [all...] |
/arch/mips/dec/ |
H A D | kn02xa-berr.c | 56 const char *kind, *agent, *cycle, *event; local 75 cycle = mreadstr; 78 cycle = invoker ? writestr : readstr; 87 kind, agent, cycle, event, address);
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H A D | kn01-berr.c | 85 const char *kind, *agent, *cycle, *event; local 130 cycle = mreadstr; 133 cycle = invoker ? writestr : readstr; 142 kind, agent, cycle, event, address);
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H A D | ecc-berr.c | 57 const char *kind, *agent, *cycle, *event; local 84 cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr; 88 cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr; 188 kind, agent, cycle, event, address);
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/arch/arm/mach-rpc/ |
H A D | dma.c | 201 static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle) argument 205 if (cycle < 188) 207 else if (cycle <= 250) 209 else if (cycle < 438)
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/arch/mips/include/asm/octeon/ |
H A D | cvmx.h | 366 * Provide current cycle counter as a return value 368 * Returns current cycle counter 373 uint64_t cycle; local 374 CVMX_RDHWR(cycle, 31); 375 return cycle; 379 * Wait for the specified number of cycle 391 * Reads a chip global cycle counter. This counts CPU cycles since 395 * Returns Global chip cycle count since chip reset.
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/arch/cris/arch-v32/lib/ |
H A D | checksumcopy.S | 32 addoq -10*4, $acr, $acr ; loop counter in latency cycle
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/arch/cris/arch-v32/mm/ |
H A D | mmu.S | 92 ; (The pipeline stalls for one cycle; $sp used as address in the next cycle.)
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/arch/powerpc/kvm/ |
H A D | Kconfig | 111 Calculate elapsed time for every exit/enter cycle. A per-vcpu
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/arch/cris/arch-v10/kernel/ |
H A D | head.S | 478 1: move.b [R_DMA_CH6_CMD],$r0 ; wait for reset cycle to finish 483 1: move.b [R_DMA_CH7_CMD],$r0 ; wait for reset cycle to finish 493 1: move.b [R_DMA_CH8_CMD],$r0 ; wait for reset cycle to finish 498 1: move.b [R_DMA_CH9_CMD],$r0 ; wait for reset cycle to finish
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/arch/ |
H A D | Kconfig | 187 subsystem. Also has support for calculating CPU cycle events
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/arch/sh/kernel/cpu/sh5/ |
H A D | switchto.S | 106 ! do this early as pta->gettr has no pipeline forwarding (=> 5 cycle latency)
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/arch/sh/lib/ |
H A D | memcpy-sh4.S | 174 mov r6, r0 ! 5 MT (0 cycle latency) 183 mov r4, r0 ! 5 MT (0 cycle latency) 196 ! cycle counts for differnet sizes using byte-at-a-time vs. optimised):
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