Searched refs:enable (Results 1 - 25 of 348) sorted by relevance

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/arch/arm/mach-s5p64x0/include/mach/
H A Ds5p64x0-clock.h22 extern int s5p64x0_epll_enable(struct clk *clk, int enable);
30 extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
31 extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
32 extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
33 extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
34 extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
35 extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
37 extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
/arch/arm/mach-w90x900/
H A Dclock.h15 void nuc900_clk_enable(struct clk *clk, int enable);
16 void nuc900_subclk_enable(struct clk *clk, int enable);
21 void (*enable)(struct clk *, int enable); member in struct:clk
26 .enable = nuc900_clk_enable, \
32 .enable = nuc900_subclk_enable, \
H A Dclock.c38 (clk->enable)(clk, 1);
53 (clk->enable)(clk, 0);
64 void nuc900_clk_enable(struct clk *clk, int enable) argument
71 if (enable)
79 void nuc900_subclk_enable(struct clk *clk, int enable) argument
86 if (enable)
/arch/arm/mach-exynos/
H A Dclock-exynos4.h26 extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
27 extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
28 extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
H A Dclock-exynos4.c121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) argument
123 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) argument
128 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) argument
133 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) argument
138 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) argument
143 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
146 exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) argument
151 exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) argument
156 exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) argument
161 exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) argument
166 exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) argument
171 exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) argument
176 exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) argument
181 exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) argument
186 exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) argument
191 exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) argument
196 exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) argument
201 exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) argument
206 exynos4_clk_dac_ctrl(struct clk *clk, int enable) argument
[all...]
H A Dclock-exynos5.c60 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable) argument
62 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
65 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable) argument
67 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
70 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) argument
72 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
75 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable) argument
77 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
80 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable) argument
82 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
85 exynos5_clk_ip_core_ctrl(struct clk *clk, int enable) argument
90 exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable) argument
95 exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable) argument
100 exynos5_clk_block_ctrl(struct clk *clk, int enable) argument
105 exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable) argument
110 exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable) argument
115 exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable) argument
120 exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable) argument
125 exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable) argument
[all...]
/arch/um/include/shared/
H A Dlongjmp.h16 volatile int enable; \
17 enable = get_signals(); \
20 set_signals(enable); \
/arch/arm/plat-omap/include/plat/
H A Dflash.h15 extern void omap1_set_vpp(struct platform_device *pdev, int enable);
H A Dmenelaus.h19 extern int menelaus_set_mmc_opendrain(int slot, int enable);
20 extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
27 extern int menelaus_set_slot_sel(int enable);
41 extern int menelaus_set_regulator_sleep(int enable, u32 val);
/arch/mips/bcm63xx/
H A Dclk.c34 static void bcm_hwclock_set(u32 mask, int enable) argument
39 if (enable)
49 static void enet_misc_set(struct clk *clk, int enable) argument
62 bcm_hwclock_set(mask, enable);
70 * Ethernet MAC clocks: only revelant on 6358, silently enable misc
73 static void enetx_set(struct clk *clk, int enable) argument
75 if (enable)
87 bcm_hwclock_set(mask, enable);
104 static void ephy_set(struct clk *clk, int enable) argument
108 bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
119 enetsw_set(struct clk *clk, int enable) argument
147 pcm_set(struct clk *clk, int enable) argument
161 usbh_set(struct clk *clk, int enable) argument
176 spi_set(struct clk *clk, int enable) argument
197 xtm_set(struct clk *clk, int enable) argument
[all...]
/arch/arm/plat-s3c24xx/
H A Ds3c2410-clock.c48 int s3c2410_clkcon_enable(struct clk *clk, int enable) argument
55 if (enable)
68 static int s3c2410_upll_enable(struct clk *clk, int enable) argument
73 if (enable)
82 if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
94 .enable = s3c2410_clkcon_enable,
99 .enable = s3c2410_clkcon_enable,
104 .enable = s3c2410_clkcon_enable,
109 .enable = s3c2410_clkcon_enable,
114 .enable
[all...]
/arch/arm/mach-s5pc100/
H A Dclock.c323 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable) argument
325 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
328 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable) argument
330 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
333 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable) argument
335 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
338 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable) argument
340 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
343 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable) argument
345 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
348 s5pc100_d1_2_ctrl(struct clk *clk, int enable) argument
353 s5pc100_d1_3_ctrl(struct clk *clk, int enable) argument
358 s5pc100_d1_4_ctrl(struct clk *clk, int enable) argument
363 s5pc100_d1_5_ctrl(struct clk *clk, int enable) argument
368 s5pc100_sclk0_ctrl(struct clk *clk, int enable) argument
373 s5pc100_sclk1_ctrl(struct clk *clk, int enable) argument
[all...]
/arch/arm/plat-mxc/include/mach/
H A Dimx-uart.h29 void (*irda_enable)(int enable);
/arch/arm/plat-samsung/include/plat/
H A Dpd.h15 int (*enable)(struct device *dev); member in struct:samsung_pd_info
H A Dclock.h29 * enable in struct clk.
54 int (*enable)(struct clk *, int enable); member in struct:clk
102 extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
135 extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
136 extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
137 extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
141 extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_cs.h8 int bcm63xx_set_cs_status(unsigned int cs, int enable);
/arch/x86/kernel/acpi/realmode/
H A Dwakemain.c12 u8 enable; local
15 enable = 0x00; /* Turn off speaker */
26 enable = 0x03; /* Turn on speaker */
30 outb(enable, 0x61); /* Enable timer 2 output to speaker */
/arch/arm/mach-omap1/
H A Dflash.c18 void omap1_set_vpp(struct platform_device *pdev, int enable) argument
23 if (enable)
/arch/arm/mach-s5pv210/
H A Dclock.c148 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) argument
150 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
153 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable) argument
155 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
158 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable) argument
160 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
163 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) argument
165 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
168 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) argument
170 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
173 s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) argument
178 s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable) argument
183 exynos4_clk_dac_ctrl(struct clk *clk, int enable) argument
[all...]
/arch/arm/mach-s3c24xx/
H A Dcommon-s3c2443.c31 static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable) argument
36 if (enable)
45 int s3c2443_clkcon_enable_h(struct clk *clk, int enable) argument
47 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
50 int s3c2443_clkcon_enable_p(struct clk *clk, int enable) argument
52 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
55 int s3c2443_clkcon_enable_s(struct clk *clk, int enable) argument
57 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
337 .enable = s3c2443_clkcon_enable_s,
351 .enable
[all...]
/arch/arm/mach-s5p64x0/
H A Dclock-s5p6440.c137 .enable = s5p64x0_mem_ctrl,
142 .enable = s5p64x0_hclk0_ctrl,
147 .enable = s5p64x0_hclk0_ctrl,
153 .enable = s5p64x0_hclk0_ctrl,
159 .enable = s5p64x0_hclk0_ctrl,
165 .enable = s5p64x0_hclk0_ctrl,
171 .enable = s5p64x0_hclk0_ctrl,
176 .enable = s5p64x0_hclk0_ctrl,
181 .enable = s5p64x0_hclk0_ctrl,
186 .enable
[all...]
H A Dclock-s5p6450.c180 .enable = s5p64x0_hclk0_ctrl,
186 .enable = s5p64x0_hclk0_ctrl,
192 .enable = s5p64x0_hclk0_ctrl,
198 .enable = s5p64x0_hclk0_ctrl,
204 .enable = s5p64x0_hclk0_ctrl,
209 .enable = s5p64x0_hclk0_ctrl,
214 .enable = s5p64x0_hclk1_ctrl,
219 .enable = s5p64x0_pclk_ctrl,
224 .enable = s5p64x0_pclk_ctrl,
229 .enable
[all...]
/arch/arm/mach-s3c64xx/
H A Dclock.c61 static int clk_48m_ctrl(struct clk *clk, int enable) argument
70 if (enable)
84 .enable = clk_48m_ctrl,
94 int enable)
101 if (enable)
110 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable) argument
112 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
115 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable) argument
117 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
120 int s3c64xx_sclk_ctrl(struct clk *clk, int enable) argument
92 s3c64xx_gate(void __iomem *reg, struct clk *clk, int enable) argument
[all...]
/arch/arm/mach-omap2/
H A Dclock34xx.c56 .enable = omap2_dflt_clk_enable,
63 .enable = omap2_dflt_clk_enable,
100 .enable = omap2_dflt_clk_enable,
107 .enable = omap2_dflt_clk_enable,
140 .enable = omap2_dflt_clk_enable,
147 .enable = omap2_dflt_clk_enable,
/arch/arm/boot/compressed/
H A Dbig-endian.S11 orr r0, r0, #(1 << 7) @ enable big endian mode

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