Searched refs:in_le32 (Results 1 - 25 of 43) sorted by relevance

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/arch/powerpc/sysdev/
H A Dgrackle.c35 val = in_le32(bp->cfg_data);
40 (void)in_le32(bp->cfg_data);
48 val = in_le32(bp->cfg_data);
53 (void)in_le32(bp->cfg_data);
H A Dmv64x60_pic.c89 (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
102 (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
126 (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
139 (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
163 (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
178 (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE);
191 (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
277 cause = in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_SELECT_CAUSE);
282 cause = in_le32(mv64x60_gpp_reg_base +
H A Dmv64x60_udbg.c37 while(in_le32(mpsc_base + MPSC_0_CR2_OFFSET) & MPSC_CHR_2_TCS)
45 return (in_le32(mpsc_intr_cause) & MPSC_INTR_CAUSE_RCC) != 0;
H A Dfsl_pci.c596 *val = in_le32(cfg_addr);
652 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
786 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
789 if (get_immrbase() == in_le32(&in[i].tar))
790 return (u64)in_le32(&in[i].barh) << 32 |
791 in_le32(&in[i].barl);
/arch/powerpc/platforms/embedded6xx/
H A Dc2k.c75 temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0);
79 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
83 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
87 temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2);
91 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
95 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
H A Dprpmc2800.c75 temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0);
79 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
83 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
87 temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2);
91 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
95 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
/arch/powerpc/boot/
H A Dcuboot-c2k.c58 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
143 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
147 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
151 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
155 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
159 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
163 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
H A Dmpsc.c53 chr1 = in_le32((u32 *)(mpsc_base + MPSC_CHR_1)) & 0x00ff0000;
54 chr2 = in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & ~(MPSC_CHR_2_TA
66 while (in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & MPSC_CHR_2_TCS);
78 cause = in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE));
90 return (u8)((in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE))
99 while ((in_le32((u32 *)(sdma_base + SDMA_SDCM))
H A Dio.h57 static inline unsigned in_le32(const volatile unsigned *addr) function
H A Dprpmc2800.c362 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
479 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
483 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
487 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
491 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
495 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
499 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
H A Dmv64x60_i2c.c67 status = in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_STATUS))
86 return in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA)) & 0xff;
H A Dmv64x60.c185 return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data));
293 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
299 base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo))
302 size = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].size))
431 i = in_le32((u32 *)(bridge_base + offset));
519 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
523 v = in_le32((u32*)(bridge_base
H A Dcuboot-pq2.c215 if (!(in_le32(&pci_regs[0][32]) & 1)) {
227 out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
/arch/powerpc/include/asm/
H A Ddbdma.h97 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
103 while(in_le32(&((regs)->status)) & (RUN)) \
/arch/powerpc/platforms/powermac/
H A Dpic.c96 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
112 (void)in_le32(&pmac_irq_hw[i]->ack);
131 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
139 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
214 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
215 bits |= in_le32(&pmac_irq_hw[i]->level);
244 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
245 bits |= in_le32(&pmac_irq_hw[i]->level);
621 (void)in_le32(&pmac_irq_hw[0]->event);
624 (void)in_le32(
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H A Dpci.c152 } while (in_le32(hose->cfg_addr) != caddr);
184 *val = in_le32(addr);
407 *val = swap ? in_le32(addr) : in_be32(addr);
488 } while (in_le32(hose->cfg_addr) != caddr);
520 *val = in_le32(addr);
593 vendev = in_le32(bp->cfg_data);
612 magic = in_le32(bp->cfg_data);
/arch/powerpc/platforms/pasemi/
H A Diommu.c216 regword = in_le32(iob+IOB_AD_REG);
222 regword = in_le32(iob+IOBCOM_REG);
H A Dpci.c88 tmp = in_le32(addr);
139 *val = in_le32(addr);
H A Dcpufreq.c84 ret = in_le32(sdcpwr_mapbase + SDCPWR_CFGA0_REG + (astate * 0x10));
93 ret = in_le32(sdcpwr_mapbase + SDCPWR_PWST0_REG);
103 giztime = in_le32(sdcpwr_mapbase + SDCPWR_GIZTIME_REG);
H A Ddma_lib.c59 return in_le32(iob_regs+reg);
79 return in_le32(mac_regs[intf]+reg);
99 return in_le32(dma_regs+reg);
/arch/powerpc/platforms/chrp/
H A Dpci.c54 *val = in_le32(cfg_data);
148 in_le32(&Hydra->Feature_Control));
157 printk(", now %x\n", in_le32(&Hydra->Feature_Control));
H A Dsetup.c112 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
115 t = in_le32(gg2_pci_config_base+
147 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
/arch/xtensa/include/asm/
H A Dio.h179 # define in_le32(addr) _swapl(*(u32*)(addr)) macro
186 # define in_le32(addr) (*(u32*)(addr)) macro
/arch/powerpc/platforms/maple/
H A Dpci.c115 } while (in_le32(hose->cfg_addr) != caddr);
146 *val = in_le32(addr);
290 *val = in_le32(addr);
369 } while (in_le32(hose->cfg_addr) != caddr);
401 *val = in_le32(addr);
/arch/m68k/include/asm/
H A Draw_io.h40 #define in_le32(addr) \ macro

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