Searched refs:input_rate (Results 1 - 8 of 8) sorted by relevance

/arch/arm/mach-davinci/
H A Dclock.h81 u32 input_rate; member in struct:pll_data
H A Dclock.c266 rate = pll->input_rate;
310 input = pll->input_rate;
376 rate = pll->input_rate = clk->parent->rate;
H A Dtnetv107x.c684 clk->pll_data->input_rate = ref;
/arch/arm/mach-tegra/
H A Dclock.h63 unsigned long input_rate; member in struct:clk_pll_freq_table
H A Dtegra30_clocks.c897 unsigned long input_rate = clk_get_rate(c->parent); local
898 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
899 if (sel->input_rate == input_rate &&
974 unsigned long input_rate; local
1000 input_rate = clk_get_rate(c->parent);
1003 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1004 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1020 if (sel->input_rate
1206 unsigned long input_rate = clk_get_rate(c->parent); local
[all...]
H A Dtegra2_clocks.c668 unsigned long input_rate; local
673 input_rate = clk_get_rate(c->parent);
674 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
675 if (sel->input_rate == input_rate && sel->output_rate == rate) {
/arch/c6x/include/asm/
H A Dclock.h112 u32 input_rate; member in struct:pll_data
/arch/c6x/platforms/
H A Dpll.c228 rate = pll->input_rate;
280 rate = pll->input_rate = clk->parent->rate;

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