Searched refs:opcode (Results 1 - 25 of 144) sorted by relevance

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/arch/arm/nwfpe/
H A Dfpopcode.h69 abcd arithmetic opcode (TABLES 3 & 4)
191 #define MASK_CPDT 0x0c000000 /* data processing opcode */
203 /* Get the coprocessor number from the opcode. */
204 #define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8)
206 /* Get the offset from the opcode. */
207 #define getOffset(opcode) (opcode & MASK_OFFSET)
210 #define TEST_OPCODE(opcode,mask) (((opcode)
391 getTransferLength(const unsigned int opcode) argument
412 getRegisterCount(const unsigned int opcode) argument
436 getRoundingPrecision(const unsigned int opcode) argument
457 getDestinationSize(const unsigned int opcode) argument
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H A Dfpa11_cpdo.c26 unsigned int SingleCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd);
27 unsigned int DoubleCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd);
28 unsigned int ExtendedCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd);
30 unsigned int EmulateCPDO(const unsigned int opcode) argument
39 nDest = getDestinationSize(opcode);
43 roundData.mode = SetRoundingMode(opcode);
44 roundData.precision = SetRoundingPrecision(opcode);
52 if (MONADIC_INSTRUCTION(opcode))
55 nType = fpa11->fType[getFn(opcode)];
57 if (!CONSTANT_FM(opcode)) {
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H A Dfpa11.c47 int8 SetRoundingMode(const unsigned int opcode) argument
49 switch (opcode & MASK_ROUNDING_MODE) {
65 int8 SetRoundingPrecision(const unsigned int opcode) argument
68 switch (opcode & MASK_ROUNDING_PRECISION) {
96 /* Emulate the instruction in the opcode. */
97 unsigned int EmulateAll(unsigned int opcode) argument
102 printk("NWFPE: emulating opcode %08x\n", opcode);
104 code = opcode & 0x00000f00;
107 code = opcode
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H A Dfpa11_cpdt.c224 unsigned int PerformLDF(const unsigned int opcode) argument
227 unsigned int nRc = 1, write_back = WRITE_BACK(opcode);
229 pBase = (unsigned int __user *) readRegister(getRn(opcode));
230 if (REG_PC == getRn(opcode)) {
236 if (BIT_UP_SET(opcode))
237 pFinal += getOffset(opcode);
239 pFinal -= getOffset(opcode);
241 if (PREINDEXED(opcode))
246 switch (opcode & MASK_TRANSFER_LENGTH) {
248 loadSingle(getFd(opcode), pAddres
267 PerformSTF(const unsigned int opcode) argument
318 PerformLFM(const unsigned int opcode) argument
354 PerformSFM(const unsigned int opcode) argument
390 EmulateCPDT(const unsigned int opcode) argument
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H A Dfpa11.h97 extern unsigned int EmulateAll(unsigned int opcode);
99 extern unsigned int EmulateCPDT(const unsigned int opcode);
100 extern unsigned int EmulateCPDO(const unsigned int opcode);
101 extern unsigned int EmulateCPRT(const unsigned int opcode);
104 extern unsigned int PerformLDF(const unsigned int opcode);
105 extern unsigned int PerformSTF(const unsigned int opcode);
106 extern unsigned int PerformLFM(const unsigned int opcode);
107 extern unsigned int PerformSFM(const unsigned int opcode);
112 const unsigned int opcode, FPREG * rFd);
115 const unsigned int opcode, FPRE
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H A Dfpa11_cprt.c30 unsigned int PerformFLT(const unsigned int opcode);
31 unsigned int PerformFIX(const unsigned int opcode);
33 static unsigned int PerformComparison(const unsigned int opcode);
35 unsigned int EmulateCPRT(const unsigned int opcode) argument
38 if (opcode & 0x800000) {
43 return PerformComparison(opcode);
47 switch ((opcode & 0x700000) >> 20) {
49 return PerformFLT(opcode);
52 return PerformFIX(opcode);
56 writeFPSR(readRegister(getRd(opcode)));
69 PerformFLT(const unsigned int opcode) argument
112 PerformFIX(const unsigned int opcode) argument
154 PerformComparison(const unsigned int opcode) argument
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H A Dsingle_cpdo.c88 unsigned int SingleCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd) argument
94 Fm = getFm(opcode);
95 if (CONSTANT_FM(opcode)) {
103 opc_mask_shift = (opcode & MASK_ARITHMETIC_OPCODE) >> 20;
104 if (!MONADIC_INSTRUCTION(opcode)) {
105 unsigned int Fn = getFn(opcode);
/arch/blackfin/include/asm/
H A Dpseudo_instructions.h15 extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode);
16 extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode);
/arch/c6x/kernel/
H A Dmodule.c19 u32 opcode; local
26 opcode = *ip;
27 opcode &= ~(mask << shift);
28 opcode |= ((delta & mask) << shift);
29 *ip = opcode;
31 pr_debug("REL PCR_S%d[%p] dest[%p] opcode[%08x]\n",
32 maskbits, ip, (void *)dest, opcode);
53 u32 *location, opcode; local
88 opcode = *location;
89 opcode
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/arch/powerpc/include/asm/
H A Dtrace.h85 TP_PROTO(unsigned long opcode, unsigned long *args),
87 TP_ARGS(opcode, args),
90 __field(unsigned long, opcode)
94 __entry->opcode = opcode;
97 TP_printk("opcode=%lu", __entry->opcode),
104 TP_PROTO(unsigned long opcode, unsigned long retval,
107 TP_ARGS(opcode, retval, retbuf),
110 __field(unsigned long, opcode)
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/arch/x86/mm/kmemcheck/
H A DMakefile1 obj-y := error.o kmemcheck.o opcode.o pte.o selftest.o shadow.o
/arch/x86/lib/
H A Dinat.c23 /* Attribute tables are generated from opcode map */
27 insn_attr_t inat_get_opcode_attribute(insn_byte_t opcode) argument
29 return inat_primary_table[opcode];
40 insn_attr_t inat_get_escape_attribute(insn_byte_t opcode, int lpfx_id, argument
51 if (inat_has_variant(table[opcode]) && lpfx_id) {
56 return table[opcode];
79 insn_attr_t inat_get_avx_attribute(insn_byte_t opcode, insn_byte_t vex_m, argument
89 if (!inat_is_group(table[opcode]) && vex_p) {
95 return table[opcode];
/arch/powerpc/xmon/
H A Dppc-dis.c33 const struct powerpc_opcode *opcode; local
50 /* Get the major opcode of the instruction. */
53 /* Find the first match in the opcode table. We could speed this up
54 a bit by doing a binary search on the major opcode. */
57 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
66 table_op = PPC_OP (opcode->opcode);
72 if ((insn & opcode
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/arch/sh/kernel/
H A Dtraps_64.c125 opcode[31:26,20:16]. The 6 MSBs of this value index into the following
146 unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */ local
161 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
167 reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
168 major = (opcode >> 26) & 0x3f;
169 minor = (opcode >> 16) & 0xf;
197 unsigned long regno = (opcode >> 20) & 0x3f;
203 unsigned long regno = (opcode >> 4) & 0x3f;
219 /* Error trying to read opcode
299 unsigned long opcode; local
342 generate_and_check_address(struct pt_regs *regs, __u32 opcode, int displacement_not_indexed, int width_shift, __u64 *address) argument
419 misaligned_load(struct pt_regs *regs, __u32 opcode, int displacement_not_indexed, int width_shift, int do_sign_extend) argument
498 misaligned_store(struct pt_regs *regs, __u32 opcode, int displacement_not_indexed, int width_shift) argument
573 misaligned_fpu_load(struct pt_regs *regs, __u32 opcode, int displacement_not_indexed, int width_shift, int do_paired_load) argument
650 misaligned_fpu_store(struct pt_regs *regs, __u32 opcode, int displacement_not_indexed, int width_shift, int do_paired_load) argument
728 unsigned long opcode; local
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H A Dkprobes.c45 kprobe_opcode_t opcode = *(kprobe_opcode_t *) (p->addr); local
47 if (OPCODE_RTE(opcode))
50 p->opcode = opcode;
58 p->opcode = *p->addr;
70 *p->addr = p->opcode;
112 saved->opcode = 0;
119 saved->opcode = 0;
159 if (OPCODE_JSR(p->opcode) || OPCODE_JMP(p->opcode)) {
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/arch/s390/kernel/
H A Dtraps.c409 __u8 opcode[6]; local
416 if (get_user(*((__u16 *) opcode), (__u16 __user *) location))
418 if (*((__u16 *) opcode) == S390_BREAKPOINT_U16) {
428 } else if (opcode[0] == 0xb3) {
429 if (get_user(*((__u16 *) (opcode+2)), location+1))
431 signal = math_emu_b3(opcode, regs);
432 } else if (opcode[0] == 0xed) {
433 if (get_user(*((__u32 *) (opcode+2)),
436 signal = math_emu_ed(opcode, regs);
437 } else if (*((__u16 *) opcode)
477 __u8 opcode[6]; local
537 __u8 opcode[6]; local
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/arch/blackfin/kernel/
H A Dpseudodbg.c106 bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode) argument
108 int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
109 int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask);
110 int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask);
111 int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask);
114 if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode)
158 bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode) argument
163 if ((opcode & 0xFF000000) != PseudoDbg_opcode)
166 opcode >>= 16;
167 grp = ((opcode >> PseudoDbg_grp_bit
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H A Ddumpstack.c21 unsigned int opcode; local
23 if (!get_instruction(&opcode, addr))
26 if ((opcode >= 0x0060 && opcode <= 0x0067) ||
27 (opcode >= 0x0070 && opcode <= 0x0077) ||
28 (opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF))
H A Dtrace.c274 static void decode_ProgCtrl_0(unsigned int opcode) argument
276 int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
277 int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
316 pr_cont("0x%04x", opcode);
330 static void decode_BRCC_0(unsigned int opcode) argument
332 int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
333 int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
346 static void decode_CALLa_0(unsigned int opcode) argument
348 int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
372 static void decode_LoopSetup_0(unsigned int opcode) argument
399 decode_dspLDST_0(unsigned int opcode) argument
462 decode_LDST_0(unsigned int opcode) argument
520 decode_LDSTii_0(unsigned int opcode) argument
557 decode_LDSTidxI_0(unsigned int opcode) argument
589 decode_opcode(unsigned int opcode) argument
623 unsigned int opcode; local
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/arch/x86/mm/
H A Dpf_in.c119 static int get_opcode(unsigned char *addr, unsigned int *opcode) argument
125 *opcode = *(unsigned short *)addr;
128 *opcode = *addr;
135 #define CHECK_OP_TYPE(opcode, array, type) \
137 if (array[i] == opcode) { \
145 unsigned int opcode; local
153 p += get_opcode(p, &opcode);
155 CHECK_OP_TYPE(opcode, reg_rop, REG_READ);
156 CHECK_OP_TYPE(opcode, reg_wop, REG_WRITE);
157 CHECK_OP_TYPE(opcode, imm_wo
166 unsigned int opcode; local
189 unsigned int opcode; local
412 unsigned int opcode; local
466 unsigned int opcode; local
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/arch/arm/kernel/
H A Dopcodes.c46 * opcode space from v5 onwards
55 asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr) argument
57 u32 cc_bits = opcode >> 28;
/arch/mips/include/asm/
H A Dinst.h37 * func field of spec opcode.
59 * func field of spec2 opcode.
70 * func field of spec3 opcode.
200 unsigned int opcode : 6; member in struct:j_format
205 unsigned int opcode : 6; member in struct:i_format
212 unsigned int opcode : 6; member in struct:u_format
219 unsigned int opcode : 6; member in struct:c_format
227 unsigned int opcode : 6; member in struct:r_format
236 unsigned int opcode : 6; member in struct:p_format
245 unsigned int opcode member in struct:f_format
255 unsigned int opcode : 6; member in struct:ma_format
265 unsigned int opcode:6; member in struct:b_format
274 unsigned int opcode : 6; member in struct:j_format
281 unsigned int opcode : 6; member in struct:i_format
288 unsigned int opcode : 6; member in struct:u_format
296 unsigned int opcode : 6; member in struct:c_format
305 unsigned int opcode : 6; member in struct:r_format
314 unsigned int opcode : 6; member in struct:p_format
324 unsigned int opcode : 6; member in struct:f_format
334 unsigned int opcode : 6; member in struct:ma_format
340 unsigned int opcode:6; member in struct:b_format
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/arch/s390/math-emu/
H A Dmath.c1615 int math_emu_b3(__u8 *opcode, struct pt_regs * regs) { argument
1657 switch (format_table[opcode[1]]) {
1659 if (opcode[3] & 0x22)
1661 emu_store_regd((opcode[3] >> 4) & 15);
1662 emu_store_regd(((opcode[3] >> 4) & 15) + 2);
1663 emu_store_regd(opcode[3] & 15);
1664 emu_store_regd((opcode[3] & 15) + 2);
1667 jump_table[opcode[1]])
1668 (regs, opcode[3] >> 4, opcode[
1889 math_emu_ed(__u8 *opcode, struct pt_regs * regs) argument
2086 math_emu_ldr(__u8 *opcode) argument
2116 math_emu_ler(__u8 *opcode) argument
2146 math_emu_ld(__u8 *opcode, struct pt_regs * regs) argument
2159 math_emu_le(__u8 *opcode, struct pt_regs * regs) argument
2173 math_emu_std(__u8 *opcode, struct pt_regs * regs) argument
2186 math_emu_ste(__u8 *opcode, struct pt_regs * regs) argument
2200 math_emu_lfpc(__u8 *opcode, struct pt_regs *regs) argument
2215 math_emu_stfpc(__u8 *opcode, struct pt_regs *regs) argument
2227 math_emu_srnm(__u8 *opcode, struct pt_regs *regs) argument
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/arch/powerpc/platforms/pseries/
H A DhvCall_inst.c105 static void probe_hcall_entry(void *ignored, unsigned long opcode, unsigned long *args) argument
109 if (opcode > MAX_HCALL_OPCODE)
112 h = &__get_cpu_var(hcall_stats)[opcode / 4];
117 static void probe_hcall_exit(void *ignored, unsigned long opcode, unsigned long retval, argument
122 if (opcode > MAX_HCALL_OPCODE)
125 h = &__get_cpu_var(hcall_stats)[opcode / 4];
/arch/mn10300/mm/
H A Dmisalignment.c44 unsigned params, unsigned opcode,
50 unsigned opcode, unsigned long disp,
53 static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode);
105 DM0, /* data reg in opcode in bits 0-1 */
106 DM1, /* data reg in opcode in bits 2-3 */
107 DM2, /* data reg in opcode in bits 4-5 */
108 AM0, /* addr reg in opcode in bits 0-1 */
109 AM1, /* addr reg in opcode in bits 2-3 */
110 AM2, /* addr reg in opcode in bits 4-5 */
111 RM0, /* reg in opcode i
154 u_int32_t opcode; member in struct:mn10300_opcode
325 uint32_t opcode, noc, xo, xm; local
548 misalignment_addr(unsigned long *registers, unsigned long sp, unsigned params, unsigned opcode, unsigned long disp, void **_address, unsigned long **_postinc, unsigned long *_inc) argument
677 misalignment_reg(unsigned long *registers, unsigned params, unsigned opcode, unsigned long disp, unsigned long **_register) argument
741 misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode) argument
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