Searched refs:ssp0_clk (Results 1 - 3 of 3) sorted by relevance

/arch/arm/mach-mxs/
H A Dclock-mx28.c291 _CLK_GET_RATE1(ssp0_clk, SSP0)
402 _CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
503 _CLK_SET_PARENT(ssp0_clk, SSP0)
590 _DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
630 _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
664 ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
774 clk_set_parent(&ssp0_clk, &ref_io0_clk);
/arch/arm/mach-spear6xx/
H A Dclock.c576 static struct clk ssp0_clk = { variable in typeref:struct:clk
667 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
/arch/arm/mach-spear3xx/
H A Dclock.c505 static struct clk ssp0_clk = { variable in typeref:struct:clk
691 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},

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