Searched refs:t3 (Results 1 - 25 of 45) sorted by relevance

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/arch/alpha/include/asm/
H A Dswab.h26 __u64 t0, t1, t2, t3; local
33 t3 = t2 & 0x00FF00FF; /* t3 : 0000000000CC00AA */
34 t1 = t0 + t3; /* t1 : ssssssssDDCCBBAA */
H A Dregdef.h9 #define t3 $4 macro
/arch/alpha/lib/
H A Dev67-strrchr.S41 sll t5, 8, t3 # U : 00000000ch000000
45 or t5, t3, t3 # E : 00000000chch0000
50 or t2, t3, t2 # E : 0000chchchch0000
59 cmpbge zero, t2, t3 # E : bits set iff byte == c
61 andnot t3, t4, t3 # E : clear garbage from char test
67 cmovne t3, v0, t6 # E : save previous comparisons match
71 cmovne t3, t3, t
[all...]
H A Dev67-strchr.S32 and a1, 0xff, t3 # E : 00000000000000ch
36 insbl t3, 6, a3 # U : 00ch000000000000
37 or t5, t3, a1 # E : 000000000000chch
54 cmpbge zero, t1, t3 # E : bits set iff byte == c
55 or t2, t3, t0 # E : bits set iff char match or zero match
73 cmpbge zero, t1, t3 # E : bits set iff byte == c
74 or t2, t3, t0 # E :
75 cttz t3, a2 # U0 : speculative (in case we get a match)
80 and t0, t3, t1 # E : bit set iff byte was the char
H A Dstrchr.S35 cmpbge zero, t1, t3 # e0 : bits set iff byte == c
36 or t2, t3, t0 # e1 : bits set iff char match or zero match
45 cmpbge zero, t1, t3 # .. e1 : bits set iff byte == c
46 or t2, t3, t0 # e0 :
52 and t0, t3, t1 # e0 : bit set iff byte was the char
56 and t0, 0xcc, t3 # .. e1 :
59 cmovne t3, 2, t3 # e0 :
61 addq t2, t3, t2 # e0 :
H A Dstrrchr.S37 cmpbge zero, t2, t3 # e0 : bits set iff byte == c
39 andnot t3, t4, t3 # e0 : clear garbage from char test
45 cmovne t3, v0, t6 # .. e1 : save previous comparisons match
46 cmovne t3, t3, t8 # e0 :
50 cmpbge zero, t2, t3 # e0 : bits set iff byte == c
60 and t3, t4, t3 # e0 : mask out char matches after null
61 cmovne t3, t
[all...]
H A Dstrlen_user.S73 and t1, 0xcc, t3
76 cmovne t3, 2, t3
78 addq t2, t3, t2
H A Dev6-strncpy_from_user.S53 and a0, 7, t3 # E : find dest misalignment
62 addq a2, t3, a2 # E : bias count by dest misalignment
85 mskqh t1, a1, t3 # U :
91 or t0, t3, t0 # E :
238 extql t2, a1, t3 # U : extract low bits for next time
247 mov t3, t1 # E :
356 cmpbge zero, t2, t3 # E :
360 andnot t8, t3, t8 # E :
387 and t12, 0xf0, t3 # E : binary search for the address of the
393 cmovne t3,
[all...]
/arch/mips/kernel/
H A Docteon_switch.S160 dmfc2 t3, 0x0082
167 sd t3, OCTEON_CP2_3DES_KEY+16(a0)
168 dmfc2 t3, 0x0103
175 sd t3, OCTEON_CP2_AES_IV+8(a0)
176 dmfc2 t3, 0x0107
183 sd t3, OCTEON_CP2_AES_KEY+24(a0)
184 mfc0 t3, $15,0 /* Get the processor ID register */
190 beq t3, t0, 2f
195 dmfc2 t3, 0x0242
201 sd t3, OCTEON_CP2_HSH_DAT
[all...]
H A Dr2300_switch.S57 lw t3, TASK_THREAD_INFO(a0)
58 lw t0, TI_FLAGS(t3)
65 sw t0, TI_FLAGS(t3)
70 lw t0, ST_OFF(t3)
73 sw t0, ST_OFF(t3)
H A Dmcount.S113 PTR_L t3, ftrace_graph_return
114 bne t1, t3, ftrace_graph_caller
117 PTR_L t3, ftrace_graph_entry
118 bne t1, t3, ftrace_graph_caller
H A Dr4k_switch.S56 PTR_L t3, TASK_THREAD_INFO(a0)
57 LONG_L t0, TI_FLAGS(t3)
64 LONG_S t0, TI_FLAGS(t3)
69 LONG_L t0, ST_OFF(t3)
72 LONG_S t0, ST_OFF(t3)
/arch/mips/include/asm/mach-pnx8550/
H A Dkernel-entry-init.h123 mfc0 t3, CP0_CONFIG, 1
128 srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */ variable
137 srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */ variable
144 srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */ variable
145 andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */ variable
146 addiu t3, t3, 1 variable
149 multu t2, t3 /* ma
[all...]
/arch/mips/include/asm/
H A Dregdef.h33 #define t3 $11 macro
84 #define t3 $15 macro
/arch/mips/lib/
H A Dcsum_partial.S26 #undef t3
30 #define t3 $11 define
173 CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4)
184 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
185 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
186 CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
187 CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
199 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
200 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
208 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t
[all...]
H A Dmemcpy-inatomic.S127 #undef t3
131 #define t3 $11 define
234 EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
245 STORE t3, UNIT(-5)(dst)
269 EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
275 STORE t3, UNIT(3)(dst)
329 EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc)
331 EXC( LDREST t3, REST(0)(src), .Ll_exc_copy)
334 STFIRST t3, FIRST(0)(dst)
360 EXC( LDFIRST t3, FIRS
[all...]
H A Dmemcpy.S127 #undef t3
131 #define t3 $11 define
239 EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
250 EXC( STORE t3, UNIT(-5)(dst), .Ls_exc_p5u)
274 EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
281 EXC( STORE t3, UNIT(3)(dst), .Ls_exc_p1u)
336 EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc)
338 EXC( LDREST t3, REST(0)(src), .Ll_exc_copy)
342 EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc)
369 EXC( LDFIRST t3, FIRS
[all...]
/arch/mips/cavium-octeon/
H A Docteon-memcpy.S112 #undef t3
116 #define t3 $11 define
210 EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
215 EXC( STORE t3, UNIT(3)(dst), s_exc_p13u)
219 EXC( LOAD t3, UNIT(7)(src), l_exc_copy)
224 EXC( STORE t3, UNIT(7)(dst), s_exc_p9u)
229 EXC( LOAD t3, UNIT(-5)(src), l_exc_copy)
233 EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u)
237 EXC( LOAD t3, UNIT(-1)(src), l_exc_copy)
241 EXC( STORE t3, UNI
[all...]
H A Dcsrc-octeon.c85 u64 t1, t2, t3; local
95 "mflo\t%[t3]\n\t"
97 "dsrlv\t%[rv],%[t3],%[shift]\n\t"
100 : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
/arch/ia64/lib/
H A Dcopy_page.S42 .rotr t1[PIPE_DEPTH], t2[PIPE_DEPTH], t3[PIPE_DEPTH], t4[PIPE_DEPTH], \
75 (p[0]) ld8 t3[0]=[src1],16
76 (EPI) st8 [tgt1]=t3[PIPE_DEPTH-1],16
/arch/mips/dec/
H A Dint-handler.S253 1: srlv t3,t1,t2
254 2: xor t1,t3
255 and t3,t0,t1
256 beqz t3,3f
258 move t0,t3
262 srlv t3,t1,t2
/arch/mips/netlogic/common/
H A Dsmpboot.S108 mul t3, t2, t1 /* t3 = node * 0x40000 */
115 add t2, t2, t3 /* t2 <- SYS offset for node */
244 li t3, 1
245 sw t3, 0(t1)
256 nor t3, t2, zero
264 and t2, t1, t3 # mask out old thread mode
/arch/arm/mach-omap2/
H A Dgpmc-smc91x.c60 const int t3 = 10; /* Figure 12.2 read and 12.4 write */ local
75 t.oe_on = t.adv_on + t3;
83 t.we_on = t.adv_on + t3;
/arch/mips/dec/prom/
H A Dcall_o32.S66 lw t3,(t0)
68 sw t3,(t1)
/arch/mips/fw/lib/
H A Dcall_o32.S68 lw t3,(t0)
70 sw t3,(t1)

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