Searched refs:timebase (Results 1 - 25 of 117) sorted by relevance

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/arch/powerpc/boot/
H A Dpq2.c32 u32 *timebase, u32 *brgfreq)
58 if (timebase)
59 *timebase = busclk / 4;
78 void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq) argument
82 dt_fixup_cpu_clocks(corefreq, timebase, sysfreq);
95 u32 sysfreq, corefreq, timebase, brgfreq; local
97 if (!pq2_get_clocks(crystal, &sysfreq, &corefreq, &timebase, &brgfreq))
100 pq2_set_clocks(sysfreq, corefreq, timebase, brgfreq);
31 pq2_get_clocks(u32 crystal, u32 *sysfreq, u32 *corefreq, u32 *timebase, u32 *brgfreq) argument
H A Dpq2.h7 u32 *timebase, u32 *brgfreq);
8 void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq);
H A Dsimpleboot.c31 const u32 *na, *ns, *reg, *timebase; local
71 /* finally, setup the timebase */
76 timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
77 if (timebase && (size == 4))
78 timebase_period_ns = 1000000000 / *timebase;
H A Dtreeboot-currituck.c89 const u32 *timebase; local
111 timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
112 if (timebase && (size == 4))
113 timebase_period_ns = 1000000000 / *timebase;
/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts39 timebase-frequency = <100000000>;
53 timebase-frequency = <100000000>;
69 timebase-frequency = <100000000>;
85 timebase-frequency = <100000000>;
H A Dps3.dts45 * dtc expects a clock-frequency and timebase-frequency entries, so
63 timebase-frequency = <0>;
H A Dgamecube.dts41 timebase-frequency = <40500000>; /* 162MHz / 4 */
H A Diss4xx.dts37 timebase-frequency = <100000000>;
H A Dmedia5200.dts31 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
H A Dcurrituck.dts35 timebase-frequency = <100000000>; // 100Mhz
49 timebase-frequency = <100000000>; // 100Mhz
H A Dadder875-redboot.dts37 timebase-frequency = <0>;
H A Dadder875-uboot.dts37 timebase-frequency = <0>;
H A Damigaone.dts33 timebase-frequency = <0>; // 33.3 MHz, from U-boot
H A Dstorcenter.dts36 timebase-frequency = <25000000>;
H A Dwii.dts50 timebase-frequency = <60750000>; /* 243MHz / 4 */
H A Dgef_ppc9a.dts48 timebase-frequency = <0>; // From uboot
59 timebase-frequency = <0>; // From uboot
H A Dgef_sbc610.dts48 timebase-frequency = <0>; // From uboot
59 timebase-frequency = <0>; // From uboot
H A Dcharon.dts36 timebase-frequency = <0>; // from bootloader
H A Dep8248e.dts39 timebase-frequency = <0>;
H A Dep88xc.dts32 timebase-frequency = <0>;
H A DkuroboxHD.dts43 timebase-frequency = <24391680>; /* Fixed by bootloader */
/arch/powerpc/platforms/pasemi/
H A Dsetup.c77 static unsigned long timebase; variable
88 timebase = get_tb();
91 while (timebase)
99 while (!timebase)
103 set_tb(timebase >> 32, timebase & 0xffffffff);
104 timebase = 0;
/arch/powerpc/platforms/powermac/
H A Dsmp.c70 static u64 timebase; variable
304 /* No sure how timebase sync works on those, let's use SW */
367 * We can't use udelay here because the timebase is now frozen.
374 * Also, because the timebase is frozen, we must not return to the
392 timebase = get_tb();
394 while (timebase)
433 while (!timebase)
436 set_tb(timebase >> 32, timebase & 0xffffffff);
437 timebase
[all...]
/arch/powerpc/include/asm/
H A Dlppaca.h196 u64 timebase; member in struct:dtl_entry
/arch/powerpc/kernel/
H A Drtas.c69 * such as having the timebase stopped which would lockup with
1061 static u64 timebase = 0; variable
1071 timebase = get_tb();
1074 while (timebase)
1082 while (!timebase)
1085 set_tb(timebase >> 32, timebase & 0xffffffff);
1086 timebase = 0;

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