/arch/arm/mach-pxa/include/mach/ |
H A D | pata_pxa.h | 26 uint32_t dma_dreq; 28 uint32_t reg_shift; 30 uint32_t irq_flags;
|
/arch/mips/include/asm/octeon/ |
H A D | cvmx-pcieep-defs.h | 187 uint32_t u32; 189 uint32_t devid:16; 190 uint32_t vendid:16; 199 uint32_t u32; 201 uint32_t dpe:1; 202 uint32_t sse:1; 203 uint32_t rma:1; 204 uint32_t rta:1; 205 uint32_t sta:1; 206 uint32_t dev [all...] |
H A D | cvmx-pciercx-defs.h | 110 uint32_t u32; 112 uint32_t devid:16; 113 uint32_t vendid:16; 128 uint32_t u32; 130 uint32_t dpe:1; 131 uint32_t sse:1; 132 uint32_t rma:1; 133 uint32_t rta:1; 134 uint32_t sta:1; 135 uint32_t dev [all...] |
H A D | cvmx-helper-jtag.h | 39 extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
|
H A D | cvmx-sysinfo.h | 62 uint32_t stack_size; 64 uint32_t heap_size; 66 uint32_t core_mask; 68 uint32_t init_core; 74 uint32_t cpu_clock_hz; 77 uint32_t dram_data_rate_hz; 105 uint32_t dfa_ref_clock_hz; 107 uint32_t bootloader_config_flags; 150 uint32_t cpu_clock_hz);
|
H A D | cvmx-pci-defs.h | 118 uint32_t u32; 120 uint32_t reserved_18_31:14; 121 uint32_t addr_idx:14; 122 uint32_t ca:1; 123 uint32_t end_swp:2; 124 uint32_t addr_v:1; 154 uint32_t u32; 156 uint32_t devid:16; 157 uint32_t vendid:16; 169 uint32_t u3 [all...] |
/arch/mips/cavium-octeon/ |
H A D | octeon_boot.h | 29 uint32_t app_start_func_addr; 31 uint32_t k0_val; 34 uint32_t flags; /* flags */ 35 uint32_t pad; 40 uint32_t labi_signature; 41 uint32_t start_core0_addr; 42 uint32_t avail_coremask; 43 uint32_t pci_console_active; 44 uint32_t icache_prefetch_disable; 46 uint32_t start_app_add [all...] |
/arch/powerpc/include/asm/ |
H A D | hvcserver.h | 46 uint32_t unit_address; 47 uint32_t partition_ID; 52 extern int hvcs_get_partner_info(uint32_t unit_address, 54 extern int hvcs_register_connection(uint32_t unit_address, 55 uint32_t p_partition_ID, uint32_t p_unit_address); 56 extern int hvcs_free_connection(uint32_t unit_address);
|
H A D | hvconsole.h | 37 extern int hvc_get_chars(uint32_t vtermno, char *buf, int count); 38 extern int hvc_put_chars(uint32_t vtermno, const char *buf, int count);
|
/arch/tile/include/hv/ |
H A D | drv_xgbe_impl.h | 115 volatile uint32_t __packet_write; 119 uint32_t __last_packet_plus_one; 182 volatile uint32_t __buffer_write; 186 uint32_t __last_buffer; 201 uint32_t __buffer_queue[NETIO_NUM_SIZES]; 204 uint32_t __epp_location; 208 volatile uint32_t __acks_received; 210 volatile uint32_t __last_completion_rcv; 212 uint32_t __max_outstanding; 218 uint32_t __paddin [all...] |
/arch/arm/mach-bcmring/include/csp/ |
H A D | intcHw.h | 36 static inline void intcHw_irq_disable(void *basep, uint32_t mask); 37 static inline void intcHw_irq_enable(void *basep, uint32_t mask);
|
H A D | reg.h | 32 #define __REG32(x) (*((volatile uint32_t *)(x))) 43 /* uint32_t reg1; offset 0x00 */ 44 /* uint32_t reg2; offset 0x04 */ 45 /* uint32_t reg3; offset 0x08 */ 46 /* uint32_t reg4; offset 0x0c */ 48 /* uint32_t reg5; offset 0x20 */ 53 #define REG32_RSVD(start, end) uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)] 87 static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t valu [all...] |
/arch/parisc/include/asm/ |
H A D | hardware.h | 42 volatile uint32_t nothing; /* reg 0 */ 43 volatile uint32_t io_eim; 44 volatile uint32_t io_dc_adata; 45 volatile uint32_t io_ii_cdata; 46 volatile uint32_t io_dma_link; /* reg 4 */ 47 volatile uint32_t io_dma_command; 48 volatile uint32_t io_dma_address; 49 volatile uint32_t io_dma_count; 50 volatile uint32_t io_flex; /* reg 8 */ 51 volatile uint32_t io_spa_addres [all...] |
/arch/frv/include/asm/ |
H A D | mb86943a.h | 17 #define __reg_MB86943_sl_ctl *(volatile uint32_t *) (__region_CS1 + 0x00) 28 #define __reg_MB86943_ecs_ctl(N) *(volatile uint32_t *) (__region_CS1 + 0x08 + (0x08*(N))) 29 #define __reg_MB86943_ecs_range(N) *(volatile uint32_t *) (__region_CS1 + 0x20 + (0x10*(N))) 30 #define __reg_MB86943_ecs_base(N) *(volatile uint32_t *) (__region_CS1 + 0x28 + (0x10*(N))) 32 #define __reg_MB86943_sl_pci_io_range *(volatile uint32_t *) (__region_CS1 + 0x50) 33 #define __reg_MB86943_sl_pci_io_base *(volatile uint32_t *) (__region_CS1 + 0x58) 34 #define __reg_MB86943_sl_pci_mem_range *(volatile uint32_t *) (__region_CS1 + 0x60) 35 #define __reg_MB86943_sl_pci_mem_base *(volatile uint32_t *) (__region_CS1 + 0x68) 36 #define __reg_MB86943_pci_sl_io_base *(volatile uint32_t *) (__region_CS1 + 0x70) 37 #define __reg_MB86943_pci_sl_mem_base *(volatile uint32_t *) (__region_CS [all...] |
/arch/mips/include/asm/netlogic/ |
H A D | haldefs.h | 54 static inline uint32_t nlm_save_flags_kx(void) 59 static inline uint32_t nlm_save_flags_cop2(void) 64 static inline void nlm_restore_flags(uint32_t sr) 74 static inline uint32_t 75 nlm_read_reg(uint64_t base, uint32_t reg) 77 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; 83 nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) 85 volatile uint32_t *add [all...] |
/arch/s390/lib/ |
H A D | div64.c | 19 static uint32_t __div64_31(uint64_t *n, uint32_t base) 21 register uint32_t reg2 asm("2"); 22 register uint32_t reg3 asm("3"); 23 uint32_t *words = (uint32_t *) n; 24 uint32_t tmp; 76 uint32_t __div64_32(uint64_t *n, uint32_t base) 78 uint32_t [all...] |
/arch/arm/mach-bcmring/include/mach/csp/ |
H A D | tmrHw_reg.h | 56 uint32_t LoadValue; /* Load value for timer */ 57 uint32_t CurrentValue; /* Current value for timer */ 58 uint32_t Control; /* Control register */ 59 uint32_t InterruptClear; /* Interrupt clear register */ 60 uint32_t RawInterruptStatus; /* Raw interrupt status */ 61 uint32_t InterruptStatus; /* Masked interrupt status */ 62 uint32_t BackgroundLoad; /* Background load value */ 63 uint32_t padding; /* Padding register */
|
H A D | chipcHw_reg.h | 33 uint32_t ChipId; /* Chip ID */ 34 uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */ 35 uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */ 36 uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */ 37 uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */ 38 uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */ 39 uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */ 40 uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */ 41 uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */ 42 uint32_t SPICloc [all...] |
H A D | dmacHw_priv.h | 31 uint32_t sar; /* Source Address Register. 33 uint32_t dar; /* Destination Address Register. 35 uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists. 38 uint32_t sstat; /* Source Status Register */ 39 uint32_t dstat; /* Destination Status Register */ 40 uint32_t devCtl; /* Device specific control information */ 41 uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */ 54 uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */ 61 uint32_t module; /* DMA controller module (0-1) */ 62 uint32_t channe [all...] |
H A D | chipcHw_def.h | 31 typedef uint32_t chipcHw_freq; 148 uint32_t pllVcoFreqHz; /* PLL VCO frequency in Hz */ 149 uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */ 150 uint32_t busClockFreqHz; /* Bus clock frequency in Hz */ 151 uint32_t armBusRatio; /* ARM clock : Bus clock */ 152 uint32_t vpmBusRatio; /* VPM clock : Bus clock */ 153 uint32_t ddrBusRatio; /* DDR clock : Bus clock */ 224 void chipcHw_pll1Enable(uint32_t vcoFreqHz, /* [ IN ] VCO frequency in Hz */ 236 void chipcHw_pll2Enable(uint32_t vcoFreqHz /* [ IN ] VCO frequency in Hz */ 279 uint32_t fre [all...] |
/arch/mips/include/asm/vr41xx/ |
H A D | pci.h | 26 uint32_t bus_base_address; 27 uint32_t address_mask; 28 uint32_t pci_base_address; 32 uint32_t address_mask; 33 uint32_t bus_base_address; 42 uint32_t base_address; 46 uint32_t base_address; 71 uint32_t pci_clock_max;
|
/arch/tile/lib/ |
H A D | strlen_32.c | 25 const uint32_t *p = (const uint32_t *)(s_int & -4); 30 uint32_t v = *p | ((1 << (s_int << 3)) - 1); 32 uint32_t bits;
|
/arch/x86/include/asm/xen/ |
H A D | hypervisor.h | 42 static inline uint32_t xen_cpuid_base(void) 44 uint32_t base, eax, ebx, ecx, edx; 49 *(uint32_t *)(signature + 0) = ebx; 50 *(uint32_t *)(signature + 4) = ecx; 51 *(uint32_t *)(signature + 8) = edx;
|
/arch/blackfin/include/asm/ |
H A D | bfrom.h | 36 static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038; 63 static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018; 64 static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A; 65 static uint32_t (* const bfrom_OtpWrite)(uint32_t pag [all...] |
/arch/arm/mach-msm/include/mach/ |
H A D | uncompress.h | 23 #define UART_CSR (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)) 24 #define UART_TF (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c)) 26 #define UART_DM_SR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))) 27 #define UART_DM_CR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10))) 28 #define UART_DM_ISR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14))) 29 #define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40))) 30 #define UART_DM_TF (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70)))
|