/arch/arm/mach-vt8500/include/mach/ |
H A D | uncompress.h | 26 writeb(c, UART0_PHYS);
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/arch/mips/sni/ |
H A D | rm200.c | 133 * readb/writeb to access them 167 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); 169 writeb(cached_master_mask, rm200_pic_master + PIC_IMR); 182 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); 184 writeb(cached_master_mask, rm200_pic_master + PIC_IMR); 194 writeb(0x0B, rm200_pic_master + PIC_CMD); 196 writeb(0x0A, rm200_pic_master + PIC_CMD); 199 writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */ 201 writeb(0x0A, rm200_pic_slave + PIC_CMD); 240 writeb(cached_slave_mas [all...] |
/arch/m68k/platform/520x/ |
H A D | config.c | 31 writeb(0x3f, MCF_GPIO_PAR_QSPI); 58 writeb(par2, MCF_GPIO_PAR_FECI2C); 69 writeb(v | 0xf0, MCF_GPIO_PAR_FEC); 72 writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
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/arch/m68k/platform/527x/ |
H A D | config.c | 34 writeb(0x1f, MCFGPIO_PAR_QSPI); 71 writeb(v | 0xf0, MCF_IPSBAR + 0x100047); 76 writeb(v | 0xc0, MCF_IPSBAR + 0x100078); 82 writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
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/arch/m68k/platform/528x/ |
H A D | config.c | 46 writeb(port, MCF5282_GPIO_PUAPAR); 58 writeb(0xc0, MCF_IPSBAR + 0x100058); 66 writeb(0, 0x30000007); 67 writeb(0x2, 0x30000007);
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/arch/mips/cobalt/ |
H A D | console.c | 19 writeb(c, UART_BASE + UART_TX);
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H A D | reset.c | 47 writeb(RESET, RESET_PORT);
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/arch/mips/jz4740/ |
H A D | serial.c | 32 writeb(value, p->membase + (offset << p->regshift));
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H A D | reset.c | 46 writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE); 52 writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
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H A D | prom.c | 67 writeb(c, UART_REG(UART_TX));
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/arch/mips/txx9/rbtx4927/ |
H A D | irq.c | 136 writeb(v, rbtx4927_imask_addr); 145 writeb(v, rbtx4927_imask_addr); 161 writeb(0, rbtx4927_imask_addr); 163 writeb(0, rbtx4927_softint_addr);
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H A D | setup.c | 74 writeb(1, rbtx4927_pcireset_addr); 83 writeb(0, rbtx4927_pcireset_addr); 92 writeb(1, rbtx4927_pcireset_addr); 99 writeb(0, rbtx4927_pcireset_addr); 121 writeb(1, rbtx4927_pcireset_addr); 130 writeb(0, rbtx4927_pcireset_addr); 139 writeb(1, rbtx4927_pcireset_addr); 146 writeb(0, rbtx4927_pcireset_addr); 172 writeb(1, rbtx4927_softresetlock_addr); 179 writeb( [all...] |
/arch/mips/txx9/rbtx4938/ |
H A D | irq.c | 89 writeb(v, rbtx4938_imask_addr); 99 writeb(v, rbtx4938_imask_addr); 149 writeb(0, rbtx4938_imask_addr); 152 writeb(0, rbtx4938_softint_addr);
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H A D | setup.c | 32 writeb(1, rbtx4938_softresetlock_addr); 33 writeb(1, rbtx4938_sfvol_addr); 34 writeb(1, rbtx4938_softreset_addr); 53 writeb(0, rbtx4938_pcireset_addr); 62 writeb(1, rbtx4938_pcireset_addr); 71 writeb(0, rbtx4938_pcireset_addr); 78 writeb(1, rbtx4938_pcireset_addr); 201 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, 205 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, 208 writeb(read [all...] |
/arch/mips/txx9/rbtx4939/ |
H A D | irq.c | 26 writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr); 33 writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr); 81 writeb(0, rbtx4939_ien_addr); 84 writeb(0, rbtx4939_softint_addr);
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/arch/xtensa/variants/s6000/ |
H A D | gpio.c | 38 writeb(0, S6_REG_GPIO + S6_GPIO_DIR + S6_GPIO_OFFSET(off)); 50 writeb(~0, S6_REG_GPIO + S6_GPIO_DIR + rel); 51 writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + rel); 57 writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off)); 82 writeb(afsel, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL); 83 writeb(afsel >> 8, S6_REG_GPIO + S6_GPIO_BANK(1) + S6_GPIO_AFSEL); 84 writeb(afsel >> 16, S6_REG_GPIO + S6_GPIO_BANK(2) + S6_GPIO_AFSEL); 90 writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC); 97 writeb(r, S6_REG_GPIO + S6_GPIO_IE); 104 writeb( [all...] |
/arch/arm/kernel/ |
H A D | io.c | 29 writeb(*f, to); 43 writeb(c, dst);
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/arch/m68k/platform/523x/ |
H A D | config.c | 32 writeb(0x1f, MCFGPIO_PAR_QSPI); 52 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
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/arch/arm/mach-vt8500/ |
H A D | irq.c | 64 writeb(dctr, base + VT8500_IC_DCTR + irq); 80 writeb(dctr, base + VT8500_IC_DCTR + irq); 114 writeb(dctr, base + VT8500_IC_DCTR + irq); 140 writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); 168 writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); 170 writeb(0x00, sic_regbase + VT8500_IC_DCTR
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/arch/ia64/include/asm/ |
H A D | smp.h | 97 writeb(0x00, ipi_base_addr + XTP_OFFSET); /* XTP to min */ 104 writeb(0x08, ipi_base_addr + XTP_OFFSET); /* XTP normal */ 111 writeb(0x0f, ipi_base_addr + XTP_OFFSET); /* Set XTP to max */
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/arch/arm/mach-nomadik/include/mach/ |
H A D | uncompress.h | 46 writeb(c, NOMADIK_UART_DR);
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/arch/mips/loongson/common/ |
H A D | early_printk.c | 25 writeb(value, PORT(base, offset));
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/arch/tile/include/asm/ |
H A D | vga.h | 35 #define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a))
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/arch/x86/platform/mrst/ |
H A D | early_printk_mrst.c | 268 writeb(0x0, phsu + UART_FCR); 272 writeb((0x80 | lcr), phsu + UART_LCR); 273 writeb(0x18, phsu + UART_DLL); 274 writeb(lcr, phsu + UART_LCR); 277 writeb(0x8, phsu + UART_MCR); 278 writeb(0x7, phsu + UART_FCR); 279 writeb(0x3, phsu + UART_LCR); 288 writeb(0x7, phsu + UART_FCR); 307 writeb(ch, phsu + UART_TX);
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/arch/m68k/include/asm/ |
H A D | ide.h | 44 #undef writeb macro 51 #define writeb(val, port) out_8(port, val) macro
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