Searched refs:AMCC_OP_REG_MCSR (Results 1 - 8 of 8) sorted by relevance

/drivers/staging/comedi/drivers/addi-data/
H A Daddi_amcc_S5920.c89 AMCC_OP_REG_MCSR);
99 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR +
106 AMCC_OP_REG_MCSR);
112 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR +
119 AMCC_OP_REG_MCSR);
125 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR +
132 AMCC_OP_REG_MCSR);
138 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR +
145 AMCC_OP_REG_MCSR);
151 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR
[all...]
H A Daddi_amcc_S5920.h18 #define AMCC_OP_REG_MCSR 0x3c macro
H A Daddi_amcc_s5933.h92 #define AMCC_OP_REG_MCSR 0x3c macro
94 #define AMCC_OP_REG_MCSR_NVDATA (AMCC_OP_REG_MCSR + 2)
96 #define AMCC_OP_REG_MCSR_NVCMD (AMCC_OP_REG_MCSR + 3)
H A Damcc_s5933_58.h90 #define AMCC_OP_REG_MCSR 0x3c macro
91 #define AMCC_OP_REG_MCSR_NVDATA (AMCC_OP_REG_MCSR + 2) /* Data in byte 2 */
92 #define AMCC_OP_REG_MCSR_NVCMD (AMCC_OP_REG_MCSR + 3) /* Command in byte 3 */
H A Dhwdrv_apci3200.c133 AMCC_OP_REG_MCSR);
143 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR +
150 AMCC_OP_REG_MCSR);
156 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR +
163 AMCC_OP_REG_MCSR);
169 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR +
176 AMCC_OP_REG_MCSR);
182 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR +
189 AMCC_OP_REG_MCSR);
195 dw_PCIBoardEepromAddress + AMCC_OP_REG_MCSR
[all...]
H A Dhwdrv_apci3120.c420 outl(0, devpriv->i_IobaseAmcc + AMCC_OP_REG_MCSR);
425 /* outl(inl(devpriv->i_IobaseAmcc+AMCC_OP_REG_MCSR)&(~EN_A2P_TRANSFERS),
426 * devpriv->i_IobaseAmcc+AMCC_OP_REG_MCSR); stop DMA */
1145 outl(0x04000000UL, devpriv->i_IobaseAmcc + AMCC_OP_REG_MCSR);
1815 devpriv->i_IobaseAmcc + AMCC_OP_REG_MCSR);
/drivers/staging/comedi/drivers/
H A Damcc_s5933.h39 #define AMCC_OP_REG_MCSR 0x3c macro
40 #define AMCC_OP_REG_MCSR_NVDATA (AMCC_OP_REG_MCSR + 2) /* Data in byte 2 */
41 #define AMCC_OP_REG_MCSR_NVCMD (AMCC_OP_REG_MCSR + 3) /* Command in byte 3 */
H A Dadl_pci9118.c1376 outl(inl(devpriv->iobase_a + AMCC_OP_REG_MCSR) & (~EN_A2P_TRANSFERS),
1377 devpriv->iobase_a + AMCC_OP_REG_MCSR); /* stop DMA */
1386 AMCC_OP_REG_MCSR) | RESET_A2P_FLAGS | A2P_HI_PRIORITY |
1387 EN_A2P_TRANSFERS, devpriv->iobase_a + AMCC_OP_REG_MCSR);
2089 outl(inl(devpriv->iobase_a + AMCC_OP_REG_MCSR) &
2091 devpriv->iobase_a + AMCC_OP_REG_MCSR); /* stop DMA */

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