Searched refs:BIT30 (Results 1 - 21 of 21) sorted by relevance

/drivers/staging/rtl8187se/
H A Dr8180_hw.h46 #define BIT30 0x40000000 macro
551 #define RF_CHANGE_BY_HW BIT30
/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h147 #define RCR_ENCS2 BIT30
192 #define CAM_CM_SecCAMClr BIT30
H A Drtl_cam.c36 ulcommand |= BIT31|BIT30;
/drivers/staging/rtl8192e/
H A Drtl819x_Qos.h54 #define BIT30 0x40000000 macro
H A Drtllib.h149 #define RT_RF_LPS_DISALBE_2R BIT30
1884 #define RF_CHANGE_BY_HW BIT30
/drivers/staging/rtl8192u/ieee80211/
H A Drtl819x_Qos.h34 #define BIT30 0x40000000 macro
H A Dieee80211.h1765 #define RF_CHANGE_BY_HW BIT30
/drivers/staging/rtl8192u/
H A Dr8192U_hw.h144 #define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2
H A Dr8192U.h81 #define BIT30 0x40000000 macro
133 #define COMP_RESET BIT30 //for silent reset
H A Dr8192U_core.c263 ulcommand |= BIT31|BIT30;
/drivers/staging/vt6655/
H A D80211hdr.h68 #define BIT30 0x40000000 macro
H A Dhostap.c567 dwKeyIndex & ~(BIT30 | USE_KEYRSC),
H A Dwpactl.c261 dwKeyIndex & ~(BIT30 | USE_KEYRSC),
/drivers/staging/vt6656/
H A D80211hdr.h66 #define BIT30 0x40000000 macro
H A Dhostap.c564 dwKeyIndex & ~(BIT30 | USE_KEYRSC),
H A Dwpactl.c246 dwKeyIndex & ~(BIT30 | USE_KEYRSC),
/drivers/scsi/
H A Ddc395x.h45 #define BIT30 0x40000000 macro
H A Dtmscsim.h161 #define BIT30 0x40000000 macro
/drivers/scsi/lpfc/
H A Dlpfc_hw4.h693 #define LPFC_SLI4_INTR30 BIT30
/drivers/tty/
H A Dsynclink.c5763 /* Set BIT30 of Misc Control Register */
5769 info->misc_ctrl_value |= BIT30;
5780 info->misc_ctrl_value &= ~BIT30;
H A Dsynclinkmp.c5183 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5187 info->misc_ctrl_value |= BIT30;
5198 info->misc_ctrl_value &= ~BIT30;

Completed in 250 milliseconds