Searched refs:BIT8 (Results 1 - 18 of 18) sorted by relevance

/drivers/staging/vt6655/
H A Dhostap.h44 #define WLAN_RATE_24M BIT8
H A D80211hdr.h46 #define BIT8 0x00000100 macro
167 #define WLAN_GET_FC_TODS(n) ((((unsigned short)(n) << 8) & (BIT8)) >> 8)
190 #define WLAN_GET_CAP_INFO_SPECTRUMMNG(n) ((((n)) & BIT8) >> 10)
202 #define WLAN_GET_FC_TODS(n) ((((unsigned short)(n)) & (BIT8)) >> 8)
226 #define WLAN_GET_CAP_INFO_SPECTRUMMNG(n) (((n) & BIT8) >> 10)
H A Ddevice_main.c2647 (Key_info & BIT8) && (Key_info & BIT9)) { //send 2/2 key
/drivers/staging/vt6656/
H A Dhostap.h44 #define WLAN_RATE_24M BIT8
H A D80211hdr.h44 #define BIT8 0x00000100 macro
164 #define WLAN_GET_FC_TODS(n) ((((WORD)(n) << 8) & (BIT8)) >> 8)
187 #define WLAN_GET_CAP_INFO_SPECTRUMMNG(n) ((((n)) & BIT8) >> 10)
198 #define WLAN_GET_FC_TODS(n) ((((WORD)(n)) & (BIT8)) >> 8)
220 #define WLAN_GET_CAP_INFO_SPECTRUMMNG(n) (((n) & BIT8) >> 10)
H A Drxtx.c2849 (Key_info & BIT8) && (Key_info & BIT9)) { //send 2/2 key
2861 (Key_info & BIT8) && (Key_info & BIT9)) {
/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h234 #define IMR_HIGHDOK BIT8
253 #define TPPoll_HCCAQ BIT8
383 #define RRSR_24M BIT8
/drivers/scsi/
H A Dtmscsim.h183 #define BIT8 0x00000100 macro
214 #define SRB_DATA_XFER BIT8
H A Ddc395x.h67 #define BIT8 0x00000100 macro
/drivers/tty/
H A Dsynclink.c504 #define RXSTATUS_SHORT_FRAME BIT8
505 #define RXSTATUS_CODE_VIOLATION BIT8
566 #define MISCSTATUS_DSR BIT8
589 #define SICR_DSR_INACTIVE BIT8
590 #define SICR_DSR (BIT9+BIT8)
1647 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
4540 /* Note: must preserve state of BIT8 in DCAR */
4569 /* Note: must preserve state of BIT8 in DCAR */
4837 RegValue |= BIT9 + BIT8;
4839 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
[all...]
H A Dsynclink_gt.c420 #define IRQ_RXOVER BIT8
2389 if (gsr & (BIT8 << i))
4156 val |= BIT8;
4196 val |= BIT8;
4245 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4318 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4391 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
5034 if (!(*(src+1) & (BIT9 + BIT8))) {
/drivers/staging/rtl8192e/
H A Drtl819x_Qos.h32 #define BIT8 0x00000100 macro
/drivers/staging/rtl8192u/ieee80211/
H A Drtl819x_Qos.h12 #define BIT8 0x00000100 macro
/drivers/staging/rtl8192u/
H A Dr8192U_hw.h315 #define RRSR_24M BIT8
H A Dr8192U.h59 #define BIT8 0x00000100 macro
106 #define COMP_SWBW BIT8 // For bandwidth switch.
/drivers/net/wireless/rtlwifi/rtl8192de/
H A Dreg.h391 #define RRSR_24M BIT8
/drivers/scsi/lpfc/
H A Dlpfc_hw4.h671 #define LPFC_SLI4_INTR8 BIT8
/drivers/char/pcmcia/
H A Dsynclink_cs.c298 #define IRQ_TXFIFO BIT8 // transmit pool ready

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