Searched refs:CSR0_STOP (Results 1 - 7 of 7) sorted by relevance

/drivers/net/ethernet/amd/
H A Dni65.h32 #define CSR0_STOP 0x0004 /* Stop (RS) */ macro
H A Dsun3lance.c213 #define CSR0_STOP 0x0004 /* stop (RS) */ macro
332 ioaddr_probe[0] = CSR0_INIT | CSR0_STOP;
334 if(ioaddr_probe[0] != CSR0_STOP) {
359 REGA(CSR0) = CSR0_STOP;
424 REGA(CSR0) = CSR0_STOP;
438 DREG = CSR0_STOP;
532 DREG = CSR0_STOP;
589 REGA( CSR0 ) = CSR0_STOP;
717 REGA(CSR0) = CSR0_STOP;
755 REGA(CSR0) = CSR0_STOP;
[all...]
H A Datarilance.c314 #define CSR0_STOP 0x0004 /* stop (RS) */ macro
510 ioaddr[0] = CSR0_INIT | CSR0_STOP;
511 if (ioaddr[0] != CSR0_STOP) {
517 ioaddr[0] = CSR0_STOP;
518 if (ioaddr[0] != CSR0_STOP) {
538 REGA( CSR0 ) = CSR0_STOP;
668 DREG = CSR0_STOP;
741 DREG = CSR0_STOP;
875 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP |
1067 DREG = CSR0_STOP;
[all...]
H A Dam79c961a.h33 #define CSR0_STOP 0x0004 macro
H A Dam79c961a.c247 write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0_STOP);
299 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
368 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
389 stopped = read_rreg(dev->base_addr, CSR0) & CSR0_STOP;
643 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
H A Dpcnet32.c199 #define CSR0_STOP 0x4 macro
797 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
893 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
907 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
974 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
1377 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1414 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
2326 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2357 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2530 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
[all...]
H A Dni65.c273 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */
577 writereg(CSR0_CLRALL|CSR0_STOP,CSR0);
728 writedatareg(CSR0_STOP);

Completed in 75 milliseconds