Searched refs:DAVINCI_MMCIM (Results 1 - 1 of 1) sorted by relevance

/drivers/mmc/host/
H A Ddavinci_mmc.c46 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ macro
91 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
404 writel(im_val, host->base + DAVINCI_MMCIM);
942 writel(0, host->base + DAVINCI_MMCIM);
970 writel(0, host->base + DAVINCI_MMCIM);
1025 writel(0, host->base + DAVINCI_MMCIM);
1049 im_val = readl(host->base + DAVINCI_MMCIM);
1050 writel(0, host->base + DAVINCI_MMCIM);
1065 writel(im_val, host->base + DAVINCI_MMCIM);
1471 writel(0, host->base + DAVINCI_MMCIM);
[all...]

Completed in 12 milliseconds