Searched refs:DIR (Results 1 - 6 of 6) sorted by relevance

/drivers/net/wan/
H A Dhd64570.h138 #define DIR 0x14 /* DMA Interrupt Enable */ macro
139 #define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
140 #define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
/drivers/staging/iio/Documentation/
H A Diio_utils.h105 DIR *dp;
200 DIR *dp;
281 DIR *dp;
444 DIR *dp;
/drivers/net/ethernet/i825xx/
H A D3c505.c273 outb_control(adapter->hcr_val | ATTN | DIR, dev);
309 outb_control(adapter->hcr_val & ~(DMAE | TCEN | DIR), dev);
615 outb_control(adapter->hcr_val | DIR | TCEN | DMAE, dev);
667 outb_control(adapter->hcr_val & ~(DMAE | TCEN | DIR), dev);
1299 if (orig_HSR & DIR) {
1300 /* If HCR.DIR is up, we pull it down. HSR.DIR should follow. */
1303 if (inb_status(addr) & DIR) {
1309 /* If HCR.DIR is down, we pull it up. HSR.DIR shoul
[all...]
H A D3c505.h28 #define DIR 0x10 /* direction */ macro
48 /* #define DIR 0x10 direction - same as in control register */
/drivers/media/video/cpia2/
H A Dcpia2_core.c523 #define DIR(cmd) ((cmd->direction == TRANSFER_WRITE) ? "Write" : "Read") macro
539 DBG("%s Random: Register block %s\n", DIR(cmd),
547 DBG("%s Block: Register block %s\n", DIR(cmd),
555 DBG("%s Mask: Register block %s\n", DIR(cmd),
563 DBG("%s Repeat: Register block %s\n", DIR(cmd),
581 DIR(cmd), start + i, buffer[i]);
584 DIR(cmd), cmd->buffer.registers[i].index,
/drivers/tty/
H A Dsynclinkmp.c378 #define DIR 0x94 macro
2236 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2388 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
4129 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4177 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4245 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4527 write_reg(info, TXDMA + DIR, 0);
4528 write_reg(info, RXDMA + DIR, 0);

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