Searched refs:MXR_CFG (Results 1 - 4 of 4) sorted by relevance

/drivers/gpu/drm/exynos/
H A Dexynos_mixer.c165 DUMPREG(MXR_CFG);
278 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
319 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
329 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
332 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
336 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_VP_ENABLE);
823 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
826 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
866 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
867 mixer_reg_writemask(res, MXR_CFG,
[all...]
H A Dregs-mixer.h21 #define MXR_CFG 0x0004 macro
79 /* bits for MXR_CFG */
/drivers/media/video/s5p-tv/
H A Dmixer_reg.c93 mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);
223 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
225 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
241 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_VP_ENABLE);
324 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_DST_MASK);
403 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK |
484 DUMPREG(MXR_CFG);
H A Dregs-mixer.h18 #define MXR_CFG 0x0004 macro
67 /* bits for MXR_CFG */

Completed in 114 milliseconds