Searched refs:PLX_INTCSR (Results 1 - 8 of 8) sorted by relevance

/drivers/net/wireless/orinoco/
H A Dorinoco_plx.c104 #define PLX_INTCSR 0x4c /* Interrupt Control & Status Register */ macro
166 csr_reg = ioread32(card->bridge_io + PLX_INTCSR);
169 iowrite32(csr_reg, card->bridge_io + PLX_INTCSR);
170 csr_reg = ioread32(card->bridge_io + PLX_INTCSR);
/drivers/net/can/sja1000/
H A Dplx_pci.c64 #define PLX_INTCSR 0x4c /* Interrupt Control/Status */ macro
451 iowrite32(0x0, card->conf_addr + PLX_INTCSR);
585 val = ioread32(card->conf_addr + PLX_INTCSR);
590 iowrite32(val, card->conf_addr + PLX_INTCSR);
/drivers/staging/comedi/drivers/
H A Dme_daq.c67 #define PLX_INTCSR 0x4C /* PLX interrupt status register */ macro
597 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
637 value = readl(dev_private->plx_regbase + PLX_INTCSR);
640 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
650 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
H A Dme4000.h162 #define PLX_INTCSR 0x4C /* Interrupt control and status register */ macro
H A Dme4000.c794 outl(0x10, info->plx_regbase + PLX_INTCSR);
806 if (!(inl(info->plx_regbase + PLX_INTCSR) & 0x20)) {
905 me4000_outl(dev, 0x43, info->plx_regbase + PLX_INTCSR);
/drivers/net/wireless/hostap/
H A Dhostap_plx.c56 #define PLX_INTCSR 0x4c /* Interrupt Control/Status Register */ macro
516 reg = inl(plx_ioaddr + PLX_INTCSR);
517 printk(KERN_DEBUG "PLX_INTCSR=0x%x\n", reg);
520 plx_ioaddr + PLX_INTCSR);
521 if (!(inl(plx_ioaddr + PLX_INTCSR) &
/drivers/isdn/hardware/mISDN/
H A Dhfc_multi.h281 #define PLX_INTCSR 0x4c macro
H A Dhfcmulti.c2698 plx_acc = hc->plx_membase + PLX_INTCSR;
4258 plx_acc = hc->plx_membase + PLX_INTCSR;
4307 plx_acc = hc->plx_membase + PLX_INTCSR;

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