Searched refs:REG (Results 1 - 25 of 32) sorted by relevance

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/drivers/net/ethernet/apple/
H A Dmace.h13 #define REG(x) volatile unsigned char x; char x ## _pad[15] macro
16 REG(rcvfifo); /* receive FIFO */
17 REG(xmtfifo); /* transmit FIFO */
18 REG(xmtfc); /* transmit frame control */
19 REG(xmtfs); /* transmit frame status */
20 REG(xmtrc); /* transmit retry count */
21 REG(rcvfc); /* receive frame control */
22 REG(rcvfs); /* receive frame status (4 bytes) */
23 REG(fifofc); /* FIFO frame count */
24 REG(i
[all...]
/drivers/watchdog/
H A Dit8712f_wdt.c62 #define REG 0x2e /* The register to read/write */ macro
100 outb(reg, REG);
106 outb(reg, REG);
113 outb(reg++, REG);
115 outb(reg, REG);
122 outb(LDN, REG);
129 * Try to reserve REG and REG + 1 for exclusive access.
131 if (!request_muxed_region(REG, 2, NAME))
134 outb(0x87, REG);
[all...]
H A Dit87_wdt.c62 #define REG 0x2e macro
168 * Try to reserve REG and REG + 1 for exclusive access.
170 if (!request_muxed_region(REG, 2, WATCHDOG_NAME))
173 outb(0x87, REG);
174 outb(0x01, REG);
175 outb(0x55, REG);
176 outb(0x55, REG);
182 outb(0x02, REG);
184 release_region(REG,
[all...]
/drivers/regulator/
H A Dmc13783-regulator.c186 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
188 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
193 MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),
194 MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val),
213 MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),
224 MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val),
225 MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val),
226 MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val),
227 MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val),
228 MC13783_GPO_DEFINE(REG, PWGT1SP
[all...]
/drivers/block/
H A Dswim.c44 #define REG(x) unsigned char x, x ## _pad[0x200 - 1]; macro
47 REG(write_data)
48 REG(write_mark)
49 REG(write_CRC)
50 REG(write_parameter)
51 REG(write_phase)
52 REG(write_setup)
53 REG(write_mode0)
54 REG(write_mode1)
56 REG(read_dat
[all...]
H A Dswim3.c58 #define REG(x) unsigned char x; char x ## _pad[15]; macro
65 REG(data);
66 REG(timer); /* counts down at 1MHz */
67 REG(error);
68 REG(mode);
69 REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
70 REG(setup);
71 REG(control); /* writing bits clears them */
72 REG(status); /* writing bits sets them in control */
73 REG(int
[all...]
/drivers/scsi/
H A Dsun3x_esp.c42 #define dma_read32(REG) \
43 readl(esp->dma_regs + (REG))
44 #define dma_write32(VAL, REG) \
45 writel((VAL), esp->dma_regs + (REG))
47 #define dma_read32(REG) \
48 *(volatile u32 *)(esp->dma_regs + (REG))
49 #define dma_write32(VAL, REG) \
50 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
H A Dmac_esp.c48 #define esp_read8(REG) mac_esp_read8(esp, REG)
49 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG)
H A Dsun_esp.c30 #define dma_read32(REG) \
31 sbus_readl(esp->dma_regs + (REG))
32 #define dma_write32(VAL, REG) \
33 sbus_writel((VAL), esp->dma_regs + (REG))
H A Dncr53c8xx.h915 #define REG(r) REGJ (nc_, r) macro
1105 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1108 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1111 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1177 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1180 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
H A Desp_scsi.c103 #define esp_read8(REG) esp->ops->esp_read8(esp, REG)
104 #define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG)
/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-fec.c46 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
47 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
H A Dmac-fcc.c72 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
73 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
/drivers/hwmon/
H A Dsmsc47b397.c54 #define REG 0x2e /* The register to read/write */ macro
59 outb(reg, REG);
65 outb(reg, REG);
77 outb(0x55, REG);
82 outb(0xAA, REG);
162 * REG: 1C/bit, two's complement
184 * REG: count of 90kHz pulses / revolution
H A Dit87.c70 #define REG 0x2e /* The register to read/write */ macro
83 outb(reg, REG);
89 outb(reg, REG);
96 outb(reg++, REG);
98 outb(reg, REG);
105 outb(DEV, REG);
112 * Try to reserve REG and REG + 1 for exclusive access.
114 if (!request_muxed_region(REG, 2, DRVNAME))
117 outb(0x87, REG);
[all...]
H A Dsmsc47m1.c56 #define REG 0x2e /* The register to read/write */ macro
62 outb(reg, REG);
69 outb(reg, REG);
79 outb(0x55, REG);
85 outb(0xAA, REG);
H A Dasb100.c113 * REG: 16mV/bit
147 * REG: 1C/bit, two's complement
163 * REG: (6.25% duty cycle per bit)
180 * REG: 0, 1, 2, or 3 (respectively) (defaults to 1)
261 #define set_in_reg(REG, reg) \
274 asb100_write_value(client, ASB100_REG_IN_##REG(nr), \
443 #define set_temp_reg(REG, reg) \
463 asb100_write_value(client, ASB100_REG_TEMP_##REG(nr+1), \
H A Dw83l786ng.c204 #define store_in_reg(REG, reg) \
218 w83l786ng_write_value(client, W83L786NG_REG_IN_##REG(nr), \
H A Dw83781d.c273 #define store_in_reg(REG, reg) \
286 w83781d_write_value(data, W83781D_REG_IN_##REG(nr), \
378 #define store_temp_reg(REG, reg) \
393 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
397 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
/drivers/scsi/sym53c8xx_2/
H A Dsym_fw.h197 #define RADDR_1(label) (RELOC_REGISTER | REG(label))
198 #define RADDR_2(label,ofs) (RELOC_REGISTER | ((REG(label))+(ofs)))
H A Dsym_defs.h385 #define REG(r) REGJ (nc_, r) macro
585 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
588 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
591 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
657 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
660 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
/drivers/media/dvb/frontends/
H A Dstb0899_priv.h255 #define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG))
256 //#define STB0899_WRITE_S2REG(DEVICE, REG, DATA) (_stb0899_write_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG, DATA))
/drivers/isdn/hardware/eicon/
H A Ddebuglib.c61 DBG_FUNC(REG)
H A Ddebuglib.h143 DBG_DECL(REG)
197 #define DBG_REG(args) DBG_TEST(REG, args)
/drivers/video/
H A Dcontrolfb.c119 #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))

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