Searched refs:SET_BIT (Results 1 - 14 of 14) sorted by relevance

/drivers/video/kyro/
H A DSTG4000VTG.c34 tmp |= SET_BIT(8);
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2);
53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31));
157 tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1);
H A DSTG4000Ramdac.c104 tmp &= ~SET_BIT(31);
152 tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0);
161 tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0);
H A DSTG4000InitDevice.c299 tmp |= SET_BIT(14);
309 tmp |= SET_BIT(14);
317 tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0));
321 tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0));
H A DSTG4000OverlayDevice.c181 tmp |= SET_BIT(31); /* Overlay format to Planer */
293 tmp |= SET_BIT(7);
298 tmp |= SET_BIT(1); /* video stream */
H A DSTG4000Reg.h31 #define SET_BIT(n) (1<<(n)) macro
/drivers/usb/storage/
H A Drealtek_cr.c127 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
580 SET_BIT(value, 2);
585 SET_BIT(value, 7);
598 SET_BIT(value, 2);
648 SET_BIT(value, 2);
664 SET_BIT(value, 0);
666 SET_BIT(value, 2);
680 SET_BIT(value, 0);
681 SET_BIT(value, 7);
685 SET_BIT(valu
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/drivers/scsi/sym53c8xx_2/
H A Dsym_nvram.c248 #define SET_BIT 0 macro
261 case SET_BIT:
285 S24C16_set_bit(np, 1, gpreg, SET_BIT);
297 S24C16_set_bit(np, 1, gpreg, SET_BIT);
307 S24C16_set_bit(np, write_bit, gpreg, SET_BIT);
501 #undef SET_BIT macro
/drivers/staging/tidspbridge/core/
H A D_tiomap.h310 #define SET_BIT(reg, mask) (reg |= mask) macro
/drivers/staging/rts5139/
H A Drts51x_card.h831 SET_BIT(chip->lun_mc, lun);
H A Drts51x_chip.h91 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
H A Dsd_cprm.c958 SET_BIT(chip->lun_mc, lun);
/drivers/staging/rts_pstor/
H A Drtsx_chip.h332 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
H A Drtsx_scsi.c256 SET_BIT(chip->lun_mc, lun);
703 SET_BIT(chip->lun_mc, lun);
913 SET_BIT(chip->lun_mc, lun);
H A Dsd.c3835 SET_BIT(chip->lun_mc, lun);

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