Searched refs:SHADDR (Results 1 - 12 of 12) sorted by relevance

/drivers/scsi/aic7xxx/
H A Daic7xxx.seq1088 mov SCB_RESIDUAL_DATACNT[3], SHADDR;
1166 * Reload HADDR from SHADDR and setup the
1170 bmov HADDR, SHADDR, 4;
1175 mvi SHADDR call bcopy_4;
1727 * we can only ack the message after SHADDR has been saved. On these
1728 * chips, SHADDR increments with every bus transaction, even PIO.
1755 * and the SCB_DATAPTR becomes the current SHADDR.
1760 bmov SCB_DATAPTR, SHADDR, 4;
1767 mvi SHADDR call bcopy_4;
H A Daic7xxx.reg441 * manner as STCNT is counted down. SHADDR should always be used
445 register SHADDR {
H A Daic7xxx_reg.h_shipped346 #define SHADDR 0x14
H A Daic79xx.seq1368 * The SCB_DATAPTR becomes the current SHADDR.
1372 bmov SCB_DATAPTR, SHADDR, 8;
H A Daic79xx_core.c1540 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
5744 data_addr = ahd_inq(ahd, SHADDR);
9914 cur_col += printk("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9915 ahd_inl(ahd, SHADDR+4),
9916 ahd_inl(ahd, SHADDR),
H A Daic79xx.reg2578 register SHADDR {
H A Daic79xx_reg.h_shipped1898 #define SHADDR 0x60
H A Daic7xxx_core.c4212 data_addr = ahc_inl(ahc, SHADDR);
/drivers/scsi/aic7xxx_old/
H A Daic7xxx.seq344 bmov HADDR, SHADDR, 4;
902 * and the SCB DATAPTR becomes the current SHADDR.
908 bmov SCB_DATAPTR, SHADDR, 4;
914 mvi SHADDR call bcopy_4;
H A Daic7xxx_reg.h155 #define SHADDR 0x14 macro
H A Daic7xxx.reg391 * manner as STCNT is counted down. SHADDR should always be used
395 register SHADDR {
/drivers/scsi/
H A Daic7xxx_old.c4690 cur_addr = aic_inb(p, SHADDR) | (aic_inb(p, SHADDR + 1) << 8) |
4691 (aic_inb(p, SHADDR + 2) << 16) | (aic_inb(p, SHADDR + 3) << 24);
4748 * in the SHADDR register set. On the Ultra2 and later controllers
4752 * HADDR register to the SHADDR register. On non-Ultra2 controllers,
4780 aic_outb(p, cur_addr & 0xff, SHADDR);
4781 aic_outb(p, (cur_addr >> 8) & 0xff, SHADDR + 1);
4782 aic_outb(p, (cur_addr >> 16) & 0xff, SHADDR + 2);
4783 aic_outb(p, (cur_addr >> 24) & 0xff, SHADDR
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