Searched refs:bRFSI_RFENV (Results 1 - 6 of 6) sorted by relevance

/drivers/staging/rtl8192e/rtl8192e/
H A Dr8190P_rtl8256.c120 bRFSI_RFENV);
125 bRFSI_RFENV<<16);
129 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
131 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
216 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
221 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16,
H A Dr8192E_phyreg.h322 #define bRFSI_RFENV 0x10 macro
H A Dr819xE_phyreg.h343 #define bRFSI_RFENV 0x10 macro
/drivers/staging/rtl8192u/
H A Dr8190_rtl8256.c140 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
144 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
149 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
152 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
216 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
220 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
H A Dr819xU_phyreg.h316 #define bRFSI_RFENV 0x10 macro
/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h470 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ macro

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