Searched refs:bw (Results 1 - 25 of 77) sorted by relevance

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/drivers/net/wireless/bcmdhd/
H A Dbcmwifi_channels.c67 const char *band, *bw, *sb; local
71 bw = "";
87 bw = "n";
91 snprintf(buf, 6, "%d%s%s%s", channel, band, bw, sb);
100 uint channel, band, bw, ctl_sb; local
113 bw = WL_CHANSPEC_BW_20;
133 bw = WL_CHANSPEC_BW_10;
135 bw = WL_CHANSPEC_BW_40;
143 bw = WL_CHANSPEC_BW_40;
155 return (channel | band | bw | ctl_s
278 uint bw; local
286 center_chan_to_edge(uint bw) argument
294 channel_low_edge(uint center_ch, uint bw) argument
301 channel_to_sb(uint center_ch, uint ctl_ch, uint bw) argument
324 channel_to_ctl_chan(uint center_ch, uint bw, uint sb) argument
366 const char *bw; local
428 uint chspec_ch, chspec_band, bw, chspec_bw, chspec_sb; local
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/drivers/media/dvb/dvb-usb/
H A Ddtt200u-fe.c49 u8 bw = GET_VIT_ERR_CNT,b[3]; local
50 dvb_usb_generic_rw(state->d,&bw,1,b,3,0);
58 u8 bw = GET_RS_UNCOR_BLK_CNT,b[2]; local
60 dvb_usb_generic_rw(state->d,&bw,1,b,2,0);
68 u8 bw = GET_AGC, b; local
69 dvb_usb_generic_rw(state->d,&bw,1,&b,1,0);
77 u8 bw = GET_SNR,br; local
78 dvb_usb_generic_rw(state->d,&bw,1,&br,1,0);
H A Dmxl111sf-tuner.c92 u8 bw)
97 switch (bw) {
199 static int mxl1x1sf_tune_rf(struct dvb_frontend *fe, u32 freq, u8 bw) argument
206 mxl_dbg("(freq = %d, bw = 0x%x)", freq, bw);
219 reg_ctrl_array = mxl111sf_calc_phy_tune_regs(freq, bw);
281 u8 bw; local
287 bw = 0; /* ATSC */
290 bw = 1; /* US CABLE */
295 bw
91 mxl111sf_calc_phy_tune_regs(u32 freq, u8 bw) argument
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/drivers/net/wireless/brcm80211/brcmsmac/
H A Drate.h90 /* mimo bw mask */
92 /* mimo bw shift */
137 u32 bw = rspec_get_bw(rspec); local
139 return bw == PHY_TXC1_BW_40MHZ || bw == PHY_TXC1_BW_40MHZ_DUP;
238 bool mcsallow, u8 bw, u8 txstreams);
247 u8 bw);
H A Drate.c444 uint rate_mask, bool mcsallow, u8 bw, u8 txstreams)
453 rs_dflt = (bw == BRCMS_20_MHZ ?
456 rs_dflt = (bw == BRCMS_20_MHZ ?
508 void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset, u8 bw) argument
510 if (bw == BRCMS_40_MHZ)
441 brcms_c_rateset_default(struct brcms_c_rateset *rs_tgt, const struct brcms_c_rateset *rs_hw, uint phy_type, int bandtype, bool cck_only, uint rate_mask, bool mcsallow, u8 bw, u8 txstreams) argument
/drivers/media/dvb/frontends/
H A Ddib7000m.c312 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw) argument
316 if (!bw)
317 bw = 8000;
320 state->current_bandwidth = bw;
330 timf = timf * (bw / 50) / 160;
378 static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw) argument
380 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
381 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff));
382 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff));
383 dib7000m_write_word(state, 22, (u16) ( bw
390 const struct dibx000_bandwidth_config *bw = state->cfg.bw; local
423 const struct dibx000_bandwidth_config *bw = state->cfg.bw; local
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H A Dit913x-fe.c248 u8 bw; local
293 bw = 0;
296 bw = 2;
299 bw = 4;
303 bw = 6;
307 set_tuner[1].reg[0] = bw;
392 u8 bw; local
399 bw = 3;
402 bw = 0;
405 bw
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H A Ddib7000p.h14 struct dibx000_bandwidth_config *bw; member in struct:dib7000p_config
57 extern int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw);
114 static inline int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw) argument
H A Ddib7000p.c362 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw) argument
367 state->current_bandwidth = bw;
371 timf = state->cfg.bw->timf;
377 timf = timf * (bw / 50) / 160;
434 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; local
438 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw
474 dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw) argument
1158 dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw) argument
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H A Dl64781.c139 int bw; local
143 bw = 8;
146 bw = 7;
149 bw = 6;
191 ddfs_offset_fixed = 0x4000-(ppm<<16)/bw/1000000;
195 bw & 0xFFFFFF);
201 spi_bias *= bw;
H A Dmt352.c118 u32 bw,value; local
122 bw = 6;
125 bw = 7;
129 bw = 8;
135 value = 64 * bw * (1<<16) / (7 * 8);
137 dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
138 __func__, bw, adc_clock, value);
H A Dtda10048.c340 u32 bw)
351 t = bw * 10;
370 u32 bw)
385 do_div(t, bw);
396 u32 bw)
399 dprintk(1, "%s(bw=%d)\n", __func__, bw);
402 switch (bw) {
406 tda10048_set_wref(fe, state->sample_freq, bw);
407 tda10048_set_invwref(fe, state->sample_freq, bw);
339 tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz, u32 bw) argument
369 tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz, u32 bw) argument
395 tda10048_set_bandwidth(struct dvb_frontend *fe, u32 bw) argument
419 tda10048_set_if(struct dvb_frontend *fe, u32 bw) argument
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H A Ddvb-pll.c97 u32 bw = fe->dtv_property_cache.bandwidth_hz; local
98 if (bw == 7000000)
190 u32 bw = fe->dtv_property_cache.bandwidth_hz; local
191 if (bw == 8000000)
224 u32 bw = fe->dtv_property_cache.bandwidth_hz; local
225 if (bw == 7000000)
248 u32 bw = fe->dtv_property_cache.bandwidth_hz; local
249 if (bw == 8000000)
H A Ddib7000m.h17 struct dibx000_bandwidth_config *bw; member in struct:dib7000m_config
H A Dcx24113.c485 u32 bw; local
487 bw = ((c->symbol_rate/100) * roll_off) / 1000;
488 bw += (10000000/100) + 5;
489 bw /= 10;
490 bw += 1000;
491 cx24113_set_bandwidth(state, bw);
495 return cx24113_get_status(fe, &bw);
H A Dstv0900_sw.c597 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
611 intp->bw[d], demod);
613 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
980 intp->bw[demod] = stv0900_carrier_width(srate,
988 intp->bw[demod],
992 intp->bw[demod]);
1510 intp->bw[demod], demod);
1513 intp->bw[demod]);
1856 intp->bw[demod] = 2 * 36000000;
1873 intp->bw[demo
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H A Ddib3000mc.c97 static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset) argument
108 timf *= (bw / 1000);
120 state->timf = timf / (bw / 1000);
214 static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw) argument
221 switch (bw) {
261 dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0);
445 u32 bw = BANDWIDTH_TO_KHZ(ch->bandwidth_hz); local
447 dib3000mc_set_bandwidth(state, bw);
448 dib3000mc_set_timing(state, ch->transmission_mode, bw, 0);
/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb.c43 static s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill, argument
54 if (bw[i] < min_percent && bw[i])
55 min_percent = bw[i];
62 int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL);
68 max[i] = bw[i] ? (bw[i] * MAX_CREDIT)/100 : min_credit;
/drivers/media/common/tuners/
H A Dtda18271-fe.c86 u32 freq, u32 bw)
705 u32 freq, u32 bw)
739 N = freq + bw / 2;
752 N = freq + bw / 2 + 1000000;
896 struct tda18271_std_map_item *map, u32 freq, u32 bw)
901 tda_dbg("freq = %d, ifc = %d, bw = %d, agc_mode = %d, std = %d\n",
902 freq, map->if_freq, bw, map->agc_mode, map->std);
916 tda18271c1_rf_tracking_filter_calibration(fe, freq, bw);
922 ret = tda18271_channel_configuration(fe, map, freq, bw);
935 u32 bw local
84 tda18271_channel_configuration(struct dvb_frontend *fe, struct tda18271_std_map_item *map, u32 freq, u32 bw) argument
704 tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, u32 freq, u32 bw) argument
895 tda18271_tune(struct dvb_frontend *fe, struct tda18271_std_map_item *map, u32 freq, u32 bw) argument
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H A Dmxl5007t.c397 enum mxl5007t_bw_mhz bw)
401 switch (bw) {
423 u32 rf_freq, enum mxl5007t_bw_mhz bw)
432 mxl5007t_set_bw_bits(state, bw);
550 enum mxl5007t_bw_mhz bw)
556 rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
624 enum mxl5007t_bw_mhz bw; local
632 bw = MxL_BW_6MHz;
636 bw = MxL_BW_6MHz;
643 bw
396 mxl5007t_set_bw_bits(struct mxl5007t_state *state, enum mxl5007t_bw_mhz bw) argument
422 mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state, u32 rf_freq, enum mxl5007t_bw_mhz bw) argument
549 mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz, enum mxl5007t_bw_mhz bw) argument
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H A Dtda18218.c116 u32 bw = c->bandwidth_hz; local
142 if (bw <= 6000000) {
145 } else if (bw <= 7000000) {
H A Dmax2165.c150 static int max2165_set_bandwidth(struct max2165_priv *priv, u32 bw) argument
154 if (bw == 8000000)
305 static int max2165_get_bandwidth(struct dvb_frontend *fe, u32 *bw) argument
310 *bw = priv->bandwidth;
H A Dxc5000.c691 u32 bw = fe->dtv_property_cache.bandwidth_hz; local
720 switch (bw) {
742 if (bw <= 6000000) {
746 } else if (bw <= 7000000) {
756 b, bw);
796 priv->bandwidth = bw;
1011 static int xc5000_get_bandwidth(struct dvb_frontend *fe, u32 *bw) argument
1016 *bw = priv->bandwidth;
/drivers/gpu/drm/nouveau/
H A Dnouveau_encoder.h37 int nr, u32 bw, bool enhframe);
/drivers/net/wireless/ath/carl9170/
H A Dphy.c967 u32 freq, enum carl9170_bw bw)
975 switch (bw) {
1036 enum carl9170_bw bw)
1052 return &carl9170_phy_freq_params[chanidx].params[bw];
1261 enum carl9170_bw bw, struct ar9170_calctl_edges edges[])
1272 if (bw == CARL9170_BW_40_BELOW || bw == CARL9170_BW_40_ABOVE)
1292 static void carl9170_calc_ctl(struct ar9170 *ar, u32 freq, enum carl9170_bw bw) argument
1367 freq, bw, EDGES(ctl_idx, 1));
1373 if (bw
966 carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz, u32 freq, enum carl9170_bw bw) argument
1035 carl9170_get_hw_dyn_params(struct ieee80211_channel *channel, enum carl9170_bw bw) argument
1260 carl9170_get_heavy_clip(struct ar9170 *ar, u32 freq, enum carl9170_bw bw, struct ar9170_calctl_edges edges[]) argument
1429 carl9170_set_power_cal(struct ar9170 *ar, u32 freq, enum carl9170_bw bw) argument
1580 enum carl9170_bw bw; local
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