| /drivers/media/video/omap3isp/ |
| H A D | isph3a_af.c | 77 paxstart = conf->paxel.h_start << AF_HZ_START_SHIFT;
84 isp_reg_writel(af->isp, conf->iir.h_start,
211 if ((paxel_cfg->h_start < iir_cfg->h_start) ||
212 IS_OUT_OF_BOUNDS(paxel_cfg->h_start,
226 if (IS_OUT_OF_BOUNDS(iir_cfg->h_start, OMAP3ISP_AF_IIRSH_MIN,
276 if (cur_cfg->iir.h_start != user_cfg->iir.h_start) {
296 (cur_cfg->paxel.h_start != user_cfg->paxel.h_start) ||
[all...] |
| H A D | isphist.c | 112 reg_hor[c] = conf->region[c].h_start <<
320 if (user_cfg->region[c].h_start & ~ISPHIST_REG_START_END_MASK)
328 if (user_cfg->region[c].h_start > user_cfg->region[c].h_end)
386 if (cur_cfg->region[c].h_start != user_cfg->region[c].h_start)
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| /drivers/media/video/sn9c102/ |
| H A D | sn9c102_tas5110d.c | 45 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 69, local
48 err += sn9c102_write_reg(cam, h_start, 0x12);
|
| H A D | sn9c102_tas5110c1b.c | 63 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 69, local
66 err += sn9c102_write_reg(cam, h_start, 0x12);
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| H A D | sn9c102_tas5130d1b.c | 63 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 104, local
67 err += sn9c102_write_reg(cam, h_start, 0x12);
|
| H A D | sn9c102_pas202bcb.c | 177 u8 h_start = 0, local
183 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 4;
186 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 3;
192 err += sn9c102_write_reg(cam, h_start, 0x12);
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| H A D | sn9c102_hv7131d.c | 124 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 2, local
127 err += sn9c102_write_reg(cam, h_start, 0x12);
|
| H A D | sn9c102_pas106b.c | 143 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 4, local
146 err += sn9c102_write_reg(cam, h_start, 0x12);
|
| H A D | sn9c102_mi0360.c | 267 u8 h_start = 0, v_start = (u8)(rect->top - s->cropcap.bounds.top) + 1; local
271 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 0;
275 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 1;
281 err += sn9c102_write_reg(cam, h_start, 0x12);
|
| H A D | sn9c102_mi0343.c | 197 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 0, local
200 err += sn9c102_write_reg(cam, h_start, 0x12);
|
| H A D | sn9c102_hv7131r.c | 214 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 1, local
217 err += sn9c102_write_reg(cam, h_start, 0x12);
|
| H A D | sn9c102_ov7630.c | 385 u8 h_start = 0, v_start = (u8)(rect->top - s->cropcap.bounds.top) + 1; local
391 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 1;
395 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 4;
401 err += sn9c102_write_reg(cam, h_start, 0x12);
|
| H A D | sn9c102_ov7660.c | 371 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 1, local
374 err += sn9c102_write_reg(cam, h_start, 0x12);
|
| H A D | sn9c102_core.c | 1606 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left), local
1612 err += sn9c102_write_reg(cam, h_start, 0x12);
1619 PDBGG("h_start, v_start, h_size, v_size, ho_size, vo_size "
1620 "%u %u %u %u", h_start, v_start, h_size, v_size);
|
| /drivers/media/video/saa7134/ |
| H A D | saa7134-vbi.c | 56 saa_writeb(SAA7134_VBI_H_START1(task), norm->h_start & 0xff);
57 saa_writeb(SAA7134_VBI_H_START2(task), norm->h_start >> 8);
|
| H A D | saa7134-video.c | 197 .h_start = 0, \
207 .h_start = 0, \
353 .h_start = 0,
547 dev->crop_bounds.left = norm->h_start;
548 dev->crop_defrect.left = norm->h_start;
549 dev->crop_bounds.width = norm->h_stop - norm->h_start +1;
550 dev->crop_defrect.width = norm->h_stop - norm->h_start +1;
701 int h_start, h_stop, v_start, v_stop; local
705 h_start = dev->crop_current.left;
710 saa_writeb(SAA7134_VIDEO_H_START1(task), h_start
711 saa_writeb(SAA7134_VIDEO_H_START2(task), h_start >> 8); local
[all...] |
| H A D | saa7134.h | 89 unsigned int h_start; member in struct:saa7134_tvnorm
|
| /drivers/video/ |
| H A D | wm8505fb.c | 83 int h_start = info->var.left_margin; local
84 int h_end = h_start + info->var.xres;
95 writel(h_start, fbi->regbase + WMT_GOVR_TIMING_H_START);
|
| H A D | bfin-lq035q1-fb.c | 108 u32 h_start; member in struct:bfin_lq035q1fb_info
246 fbi->h_start = (7 * clocks_per_pix + cpld_pipeline_delay_cor); /* first valid pixel */
264 bfin_write_PPI_DELAY(fbi->h_start);
|
| /drivers/video/nvidia/ |
| H A D | nvidia.c | 312 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1; local
339 h_start = h_total - 5;
349 state->crtc[0x4] = Set8Bits(h_start);
386 | SetBitField(h_start, 8: 8, 3:3);
|