Searched refs:irqmask (Results 1 - 19 of 19) sorted by relevance

/drivers/ata/
H A Dpata_hpt3x2n.c495 u8 irqmask; local
544 pci_read_config_byte(dev, 0x5A, &irqmask);
545 irqmask &= ~0x10;
546 pci_write_config_byte(dev, 0x5a, irqmask);
H A Dpata_hpt37x.c827 u8 irqmask; local
919 pci_read_config_byte(dev, 0x5A, &irqmask);
920 irqmask &= ~0x10;
921 pci_write_config_byte(dev, 0x5a, irqmask);
H A Dpata_icside.c66 unsigned int irqmask; member in struct:pata_icside_info
384 info->irqmask = 1;
445 ec->irqmask = info->irqmask;
/drivers/media/rc/
H A Dwinbond-cir.c206 u8 irqmask; member in struct:wbcir_data
273 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) argument
275 if (data->irqmask == irqmask)
279 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
280 data->irqmask = irqmask;
461 status &= data->irqmask;
/drivers/scsi/arm/
H A Darxescsi.c324 ec->irqmask = CSTATUS_IRQ;
H A Dcumana_2.c450 ec->irqmask = STATUS_INT;
H A Dpowertec.c361 ec->irqmask = POWERTEC_INTR_BIT;
H A Deesox.c569 ec->irqmask = EESOX_STAT_INTR;
H A Dacornscsi.c2997 ec->irqmask = 0x0a;
/drivers/mmc/host/
H A Dmmci.c610 unsigned int datactrl, timeout, irqmask; local
658 irqmask = MCI_RXFIFOHALFFULLMASK;
666 irqmask |= MCI_RXDATAAVLBLMASK;
672 irqmask = MCI_TXFIFOHALFEMPTYMASK;
677 mmci_set_mask1(host, irqmask);
/drivers/net/ethernet/nvidia/
H A Dforcedeth.c782 u32 irqmask; member in struct:fe_priv
1101 /* In MSIX mode, a write to irqmask behaves as XOR */
3502 if (np->irqmask != NVREG_IRQMASK_CPU) {
3503 np->irqmask = NVREG_IRQMASK_CPU;
3512 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3513 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3535 if (!(np->events & np->irqmask))
3569 if (!(np->events & np->irqmask))
3598 if (!(events & np->irqmask))
3678 np->nic_poll_irq = np->irqmask;
3836 set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) argument
[all...]
/drivers/media/video/ivtv/
H A Divtv-driver.c284 itv->irqmask &= ~mask;
285 write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK);
290 itv->irqmask |= mask;
291 write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK);
H A Divtv-irq.c890 combo = ~itv->irqmask & stat;
899 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
965 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
H A Divtv-driver.h674 u32 irqmask; /* active interrupts */ member in struct:ivtv
H A Divtv-streams.c744 IVTV_DEBUG_IRQ("IRQ Mask is now: 0x%08x\n", itv->irqmask);
/drivers/ide/
H A Dicside.c426 ec->irqmask = 1;
/drivers/video/omap2/dss/
H A Ddispc.c3191 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout) argument
3202 irqmask);
3209 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3220 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, argument
3232 irqmask);
3240 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
/drivers/net/ethernet/seeq/
H A Dether3.c798 ec->irqmask = 0xf0;
/drivers/staging/comedi/drivers/
H A Dni_stc.h1443 int irqmask; \

Completed in 415 milliseconds