Searched refs:log2P (Results 1 - 8 of 8) sorted by relevance
/drivers/gpu/drm/nouveau/ |
H A D | nv40_pm.c | 110 u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P) 137 *log2P = coef.log2P; 146 int N1, N2, M1, M2, log2P; local 155 &N1, &M1, &N2, &M2, &log2P); 160 info->npll_ctrl = 0x80000100 | (log2P << 16); 163 info->npll_ctrl = 0xc0000000 | (log2P << 16); 170 &N1, &M1, NULL, NULL, &log2P); 174 info->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; 188 &N1, &M1, &N2, &M2, &log2P); 109 nv40_calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll, u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P) argument [all...] |
H A D | nouveau_calc.c | 353 bestpv->log2P = thisP; 388 int M1, N1, M2, N2, log2P; local 394 for (log2P = 0; clk && log2P < maxlog2P && clk <= (vco2 >> log2P); log2P++) 396 clkP = clk << log2P; 440 calcclkout = calcclk2 >> log2P; 452 bestpv->log2P = log2P; [all...] |
H A D | nv50_calc.c | 44 *P = pll_vals.log2P;
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H A D | nouveau_hw.c | 166 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; 182 NVWriteRAMDAC(dev, 0, reg, pv->log2P << 16 | (oldpll & 0xffff)); 224 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; 309 0xc << 28 | pv->log2P << 16; 330 Pval2 = pv->log2P + pll_lim.log2p_bias; 401 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ 402 pllvals->log2P = (pll1 >> 16) & 0x7; 477 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; 530 pv.log2P <= pll_lim.max_log2p) 538 pv.log2P [all...] |
H A D | nv50_pm.c | 367 u32 clk, int *N1, int *M1, int *log2P) 387 *log2P = coef.log2P; 366 calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll, u32 clk, int *N1, int *M1, int *log2P) argument
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H A D | nv04_crtc.c | 148 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 151 pv->N1, pv->M1, pv->log2P);
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H A D | nouveau_drv.h | 620 int log2P; member in struct:nouveau_pll_vals
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H A D | nouveau_bios.c | 693 ctrl = pll.log2P << 16; 698 ctrl |= (pll.log2P << 22);
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