Searched refs:membase (Results 1 - 25 of 121) sorted by relevance

12345

/drivers/tty/serial/
H A Dbfin_sport_uart.h34 #define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
35 #define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
36 #define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
37 #define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
38 #define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
39 #define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
51 __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
56 #define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
57 #define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
58 #define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase
[all...]
H A Dnetx-serial.c121 val = readl(port->membase + UART_CR);
122 writel(val & ~CR_TIE, port->membase + UART_CR);
128 val = readl(port->membase + UART_CR);
129 writel(val & ~CR_RIE, port->membase + UART_CR);
135 val = readl(port->membase + UART_CR);
136 writel(val | CR_MSIE, port->membase + UART_CR);
144 writel(port->x_char, port->membase + UART_DR);
158 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
164 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
173 readl(port->membase
[all...]
H A Dtimbuart.c54 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS;
55 iowrite32(ier, port->membase + TIMBUART_IER);
61 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE;
62 iowrite32(ier, port->membase + TIMBUART_IER);
76 u32 isr = ioread32(port->membase + TIMBUART_ISR);
84 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) |
87 iowrite8(ctl, port->membase + TIMBUART_CTRL);
88 iowrite32(TXBF, port->membase + TIMBUART_ISR);
96 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) {
97 u8 ch = ioread8(port->membase
[all...]
H A Dmxs-auart.c134 while (!(readl(s->port.membase + AUART_STAT) &
139 s->port.membase + AUART_DATA);
146 s->port.membase + AUART_DATA);
156 s->port.membase + AUART_INTR_CLR);
159 s->port.membase + AUART_INTR_SET);
171 c = readl(s->port.membase + AUART_DATA);
172 stat = readl(s->port.membase + AUART_STAT);
207 writel(stat, s->port.membase + AUART_STAT);
216 stat = readl(s->port.membase + AUART_STAT);
222 writel(stat, s->port.membase
[all...]
H A Dmcf.c64 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
75 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
95 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
105 writeb(pp->imr, port->membase + MCFUART_UIMR);
115 writeb(pp->imr, port->membase + MCFUART_UIMR);
125 writeb(pp->imr, port->membase + MCFUART_UIMR);
136 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
138 writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
158 writeb(MCFUART_UCR_CMDRESETRX, port->membase
[all...]
H A Dimx.c276 ucr->ucr1 = readl(port->membase + UCR1);
277 ucr->ucr2 = readl(port->membase + UCR2);
278 ucr->ucr3 = readl(port->membase + UCR3);
285 writel(ucr->ucr1, port->membase + UCR1);
286 writel(ucr->ucr2, port->membase + UCR2);
287 writel(ucr->ucr3, port->membase + UCR3);
347 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
361 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
362 temp = readl(sport->port.membase + UCR1);
364 writel(temp, sport->port.membase
[all...]
H A Dlantiq.c148 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
167 ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
170 ch = ltq_r8(port->membase + LTQ_ASC_RBUF);
171 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE)
184 port->membase + LTQ_ASC_WHBSTATE);
188 port->membase + LTQ_ASC_WHBSTATE);
193 port->membase + LTQ_ASC_WHBSTATE);
230 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) &
233 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF);
243 port->membase
[all...]
H A Damba-pl011.c188 status = readw(uap->port.membase + UART01x_FR);
193 ch = readw(uap->port.membase + UART01x_DR) |
400 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
424 writew(uap->im, uap->port.membase + UART011_IMSC);
511 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
547 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
549 writew(uap->im, uap->port.membase + UART011_IMSC);
559 writew(uap->im, uap->port.membase + UART011_IMSC);
573 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
604 writew(uap->im, uap->port.membase
[all...]
H A Damba-pl010.c82 cr = readb(uap->port.membase + UART010_CR);
84 writel(cr, uap->port.membase + UART010_CR);
92 cr = readb(uap->port.membase + UART010_CR);
94 writel(cr, uap->port.membase + UART010_CR);
102 cr = readb(uap->port.membase + UART010_CR);
104 writel(cr, uap->port.membase + UART010_CR);
112 cr = readb(uap->port.membase + UART010_CR);
114 writel(cr, uap->port.membase + UART010_CR);
122 status = readb(uap->port.membase + UART01x_FR);
124 ch = readb(uap->port.membase
[all...]
H A Daltera_jtaguart.c68 return (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) &
87 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
96 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
105 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
131 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) &
153 writel(port->x_char, port->membase + ALTERA_JTAGUART_DATA_REG);
161 count = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) &
170 port->membase + ALTERA_JTAGUART_DATA_REG);
181 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
192 isr = (readl(port->membase
[all...]
H A Duartlite.c80 ch = ioread32be(port->membase + ULITE_RX);
125 iowrite32be(port->x_char, port->membase + ULITE_TX);
134 iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
151 int stat = ioread32be(port->membase + ULITE_STATUS);
172 ret = ioread32be(port->membase + ULITE_STATUS);
195 ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
225 port->membase + ULITE_CONTROL);
226 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
233 iowrite32be(0, port->membase + ULITE_CONTROL);
234 ioread32be(port->membase
[all...]
H A Dsamsung.h70 #define portaddr(port, reg) ((port)->membase + (reg))
71 #define portaddrl(port, reg) ((unsigned long *)((port)->membase + (reg)))
H A Dpch_uart.c223 void __iomem *membase; member in struct:eg20t_port
329 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
331 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
333 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
335 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
337 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
339 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
342 ioread8(priv->membase + PCH_UART_BRCSR));
344 lcr = ioread8(priv->membase + UART_LCR);
345 iowrite8(PCH_UART_LCR_DLAB, priv->membase
1405 void __iomem *membase; local
[all...]
/drivers/isdn/hisax/
H A Dtelespci.c183 return (readisac(cs->hw.teles0.membase, offset));
189 writeisac(cs->hw.teles0.membase, offset, value);
195 read_fifo_isac(cs->hw.teles0.membase, data, size);
201 write_fifo_isac(cs->hw.teles0.membase, data, size);
207 return (readhscx(cs->hw.teles0.membase, hscx, offset));
213 writehscx(cs->hw.teles0.membase, hscx, offset, value);
220 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
221 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
222 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
223 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, n
[all...]
H A Dteles0.c100 return (readisac(cs->hw.teles0.membase, offset));
106 writeisac(cs->hw.teles0.membase, offset, value);
112 read_fifo_isac(cs->hw.teles0.membase, data, size);
118 write_fifo_isac(cs->hw.teles0.membase, data, size);
124 return (readhscx(cs->hw.teles0.membase, hscx, offset));
130 writehscx(cs->hw.teles0.membase, hscx, offset, value);
137 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
138 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
139 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
140 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, n
[all...]
/drivers/atm/
H A Didt77252.h352 void __iomem *membase; /* SAR's memory base address */ member in struct:idt77252_dev
438 #define SAR_REG_DR0 (card->membase + 0x00)
439 #define SAR_REG_DR1 (card->membase + 0x04)
440 #define SAR_REG_DR2 (card->membase + 0x08)
441 #define SAR_REG_DR3 (card->membase + 0x0C)
442 #define SAR_REG_CMD (card->membase + 0x10)
443 #define SAR_REG_CFG (card->membase + 0x14)
444 #define SAR_REG_STAT (card->membase + 0x18)
445 #define SAR_REG_RSQB (card->membase + 0x1C)
446 #define SAR_REG_RSQT (card->membase
[all...]
/drivers/gpio/
H A Dgpio-timberdale.c46 void __iomem *membase; member in struct:timbgpio
60 reg = ioread32(tgpio->membase + offset);
67 iowrite32(reg, tgpio->membase + offset);
83 value = ioread32(tgpio->membase + TGPIOVAL);
120 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
132 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
148 ver = ioread32(tgpio->membase + TGPIO_VER);
152 lvr = ioread32(tgpio->membase + TGPIO_LVR);
153 flr = ioread32(tgpio->membase + TGPIO_FLR);
155 bflr = ioread32(tgpio->membase
[all...]
/drivers/input/keyboard/
H A Dlocomokbd.c87 static inline void locomokbd_charge_all(unsigned long membase) argument
89 locomo_writel(0x00FF, membase + LOCOMO_KSC);
92 static inline void locomokbd_activate_all(unsigned long membase) argument
96 locomo_writel(0, membase + LOCOMO_KSC);
97 r = locomo_readl(membase + LOCOMO_KIC);
99 locomo_writel(r, membase + LOCOMO_KIC);
102 static inline void locomokbd_activate_col(unsigned long membase, int col) argument
109 locomo_writel(nbset, membase + LOCOMO_KSC);
112 static inline void locomokbd_reset_col(unsigned long membase, int col) argument
117 locomo_writel(nbset, membase
132 unsigned long membase = locomokbd->base; local
[all...]
/drivers/net/ethernet/sfc/
H A Dio.h68 __raw_writeq((__force u64)value, efx->membase + reg);
72 return (__force __le64)__raw_readq(efx->membase + reg);
79 __raw_writel((__force u32)value, efx->membase + reg);
83 return (__force __le32)__raw_readl(efx->membase + reg);
111 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase, argument
123 __raw_writeq((__force u64)value->u64[0], membase + addr);
125 __raw_writel((__force u32)value->u32[0], membase + addr);
126 __raw_writel((__force u32)value->u32[1], membase + addr + 4);
163 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase, argument
171 value->u64[0] = (__force __le64)__raw_readq(membase
[all...]
/drivers/tty/serial/8250/
H A D8250_early.c55 return readb(port->membase + offset);
57 return readl(port->membase + (offset << 2));
69 writeb(value, port->membase + offset);
72 writel(value, port->membase + (offset << 2));
173 port->membase =
175 port->membase += port->mapbase & ~PAGE_MASK;
177 port->membase = ioremap_nocache(port->mapbase, 64);
178 if (!port->membase) {
231 if (device->port.membase || device->port.iobase)
271 if (!device->port.membase
[all...]
H A D8250_dw.c41 writeb(value, p->membase + offset);
48 return readb(p->membase + offset);
59 writel(value, p->membase + offset);
66 return readl(p->membase + offset);
/drivers/isdn/hardware/avm/
H A Dt1pci.c73 card->membase = p->membase;
83 card->mbase = ioremap(card->membase, 64);
86 card->membase);
134 card->port, card->irq, card->membase);
183 cinfo->card ? cinfo->card->membase : 0
204 param.membase = pci_resource_start(dev, 0);
207 param.port, param.irq, param.membase);
212 param.port, param.irq, param.membase);
/drivers/dma/
H A Dtimb_dma.c84 void __iomem *membase; member in struct:timb_dma_chan
101 void __iomem *membase; member in struct:timb_dma
130 ier = ioread32(td->membase + TIMBDMA_IER);
134 iowrite32(ier, td->membase + TIMBDMA_IER);
148 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id);
150 iowrite32(isr, td->membase + TIMBDMA_ISR);
236 "td_chan: %p, chan: %d, membase: %p\n",
237 td_chan, td_chan->chan.chan_id, td_chan->membase);
242 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR);
243 iowrite32(td_desc->txd.phys, td_chan->membase
[all...]
/drivers/misc/ibmasm/
H A Duart.c55 uport.membase = iomem_base;
/drivers/net/irda/
H A Dbfin_sir.h40 unsigned char __iomem *membase; member in struct:bfin_sir_port
85 #define port_membase(port) (((struct bfin_sir_port *)(port))->membase)

Completed in 519 milliseconds

12345