Searched refs:pixclk (Results 1 - 6 of 6) sorted by relevance

/drivers/media/video/
H A Dmt9v022.c708 u16 pixclk = 0; local
723 pixclk |= 0x10;
726 pixclk |= 0x1;
729 pixclk |= 0x2;
731 ret = reg_write(client, MT9V022_PIXCLK_FV_LV, pixclk);
742 dev_dbg(&client->dev, "Calculated pixclk 0x%x, chip control 0x%x\n",
743 pixclk, mt9v022->chip_control);
/drivers/video/
H A Dbroadsheetfb.c48 u16 pixclk; member in struct:panel_info
63 .pixclk = 6,
75 .pixclk = 14,
87 .pixclk = 3,
797 args[4] = panel_table[par->panel_index].pixclk;
H A Dfb-puv3.c473 u32 pixclk = 0; local
485 pixclk = unifb_modes[i].pixclock;
495 if (pixclk != 0) {
496 if (clk_set_rate(clk_vga, pixclk)) { /* set clock failed */
H A Ds3c-fb.c194 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
195 * @lcd_clk: The clk (sclk) feeding pixclk.
346 static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk) argument
358 tmp *= pixclk;
363 dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
364 pixclk, clk, result, clk / result);
1116 u64 pixclk = 1000000000000ULL; local
1125 do_div(pixclk, div);
1127 mode->pixclock = pixclk;
H A Dnuc900fb.c71 unsigned long pixclk)
76 /* pixclk is in picseconds. our clock is in Hz*/
77 /* div = (clk * pixclk)/10^12 */
78 div = (unsigned long long)clk * pixclk;
82 dev_dbg(fbi->dev, "pixclk %ld, divisor is %lld\n", pixclk, div);
70 nuc900fb_calc_pixclk(struct nuc900fb_info *fbi, unsigned long pixclk) argument
H A Ds3c2410fb.c89 * calculate divisor for clk->pixclk
92 unsigned long pixclk)
97 /* pixclk is in picoseconds, our clock is in Hz
102 div = (unsigned long long)clk * pixclk;
106 dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
91 s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi, unsigned long pixclk) argument

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