Searched refs:rOFDM0_XDAGCCore1 (Results 1 - 8 of 8) sorted by relevance

/drivers/staging/rtl8192u/
H A Dr819xU_phy.c645 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
866 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
1718 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
1732 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1745 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
H A Dr8192U_dm.c1773 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1815 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
2190 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
2253 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
2260 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
2453 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
H A Dr819xU_phyreg.h133 #define rOFDM0_XDAGCCore1 0xc68 macro
/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phy.c460 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
631 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
1332 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1,
1354 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1373 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask,
H A Drtl_dm.c1607 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1644 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1848 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
1880 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
1885 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
1989 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
H A Dr8192E_phyreg.h149 #define rOFDM0_XDAGCCore1 0xc68 macro
H A Dr819xE_phyreg.h154 #define rOFDM0_XDAGCCore1 0xc68 macro
/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h213 #define rOFDM0_XDAGCCore1 0xc68 macro

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