Searched refs:readw (Results 1 - 25 of 213) sorted by relevance

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/drivers/scsi/qla4xxx/
H A Dql4_dbg.c47 readw(&ha->reg->mailbox[i]));
52 readw(&ha->reg->flash_address));
55 readw(&ha->reg->flash_data));
58 readw(&ha->reg->ctrl_status));
63 readw(&ha->reg->u1.isp4010.nvram));
67 readw(&ha->reg->u1.isp4022.intr_mask));
70 readw(&ha->reg->u1.isp4022.nvram));
73 readw(&ha->reg->u1.isp4022.semaphore));
77 readw(&ha->reg->req_q_in));
80 readw(
[all...]
/drivers/net/tokenring/
H A Dlanstreamer.c454 writew(readw(streamer_mmio + BCTL) | BCTL_SOFTRESET, streamer_mmio + BCTL);
459 writew(readw(streamer_mmio + BCTL) & ~BCTL_SOFTRESET,
463 printk("BCTL: %x\n", readw(streamer_mmio + BCTL));
464 printk("GPR: %x\n", readw(streamer_mmio + GPR));
465 printk("SISRMASK: %x\n", readw(streamer_mmio + SISR_MASK));
467 writew(readw(streamer_mmio + BCTL) | (BCTL_RX_FIFO_8 | BCTL_TX_FIFO_8), streamer_mmio + BCTL );
470 writew(readw(streamer_mmio + GPR) | GPR_AUTOSENSE,
507 printk("GPR = %x\n", readw(streamer_mmio + GPR));
512 while (!((readw(streamer_mmio + SISR)) & SISR_SRB_REPLY)) {
524 misr = readw(streamer_mmi
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H A Dolympic.c326 printk("GPR: %x\n",readw(olympic_mmio+GPR));
336 writew(readw(olympic_mmio+GPR)|GPR_AUTOSENSE,olympic_mmio+GPR);
349 writew(readw(olympic_mmio+GPR)|GPR_NEPTUNE_BF,olympic_mmio+GPR);
352 printk("GPR = %x\n",readw(olympic_mmio + GPR) ) ;
384 writel(readw(olympic_mmio+LAPWWO),olympic_mmio+LAPA);
390 init_srb=olympic_priv->olympic_lap + ((readw(olympic_mmio+LAPWWO)) & (~0xf800));
401 if(readw(init_srb+6)) {
402 printk(KERN_INFO "tokenring card initialization failed. errorcode : %x\n",readw(init_srb+6));
414 uaa_addr=swab16(readw(init_srb+8));
429 olympic_priv->olympic_addr_table_addr = swab16(readw(init_sr
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H A D3c359.c222 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
230 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
238 return readw(xl_mmio + MMIO_MACDATA) ;
254 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
262 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
274 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
439 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
465 printk(KERN_INFO "Read from PMBAR = %04x\n", readw(xl_mmio + MMIO_MACDATA));
468 if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
473 result_16 = readw(xl_mmi
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/drivers/scsi/arm/
H A Dcumana_1.c140 *laddr++ = readw(dma) | (readw(dma) << 16);
141 *laddr++ = readw(dma) | (readw(dma) << 16);
142 *laddr++ = readw(dma) | (readw(dma) << 16);
143 *laddr++ = readw(dma) | (readw(dma) << 16);
144 *laddr++ = readw(dma) | (readw(dm
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H A Doak.c65 while (((status = readw(base + STAT)) & 0x100)==0);
81 while (((status = readw(base + STAT)) & 0x100)==0)
99 b = (unsigned long) readw(base + DATA);
/drivers/watchdog/
H A Dcoh901327_wdt.c95 val = readw(virtbase + U300_WDOG_D2R);
119 (void) readw(virtbase + U300_WDOG_CR);
120 val = readw(virtbase + U300_WDOG_D2R);
136 val = readw(virtbase + U300_WDOG_D2R);
146 val = readw(virtbase + U300_WDOG_D2R);
196 val = readw(virtbase + U300_WDOG_CR);
198 val = readw(virtbase + U300_WDOG_CR);
225 val = readw(virtbase + U300_WDOG_IER);
309 val = readw(virtbase + U300_WDOG_SR);
327 val = readw(virtbas
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/drivers/tty/
H A Dmoxa.c242 while (readw(ofsAddr + FuncCode) != 0)
245 if (readw(ofsAddr + FuncCode) != 0)
267 ret = readw(ofsAddr + FuncArg);
277 rptr = readw(ofsAddr + RXrptr);
278 wptr = readw(ofsAddr + RXwptr);
279 mask = readw(ofsAddr + RX_mask);
486 tmp = readw(baseAddr + C218_key);
491 tmp = readw(baseAddr + C218_key);
496 tmp = readw(baseAddr + C320_key);
499 tmp = readw(baseAdd
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/drivers/rtc/
H A Drtc-mxc.c96 day = readw(ioaddr + RTC_DAYR);
97 hr_min = readw(ioaddr + RTC_HOURMIN);
98 sec = readw(ioaddr + RTC_SECOND);
101 day = readw(ioaddr + RTC_DAYALARM);
102 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
103 sec = readw(ioaddr + RTC_ALRM_SEC);
173 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
188 reg = readw(ioaddr + RTC_RTCIENR);
210 status = readw(ioaddr + RTC_RTCISR) & readw(ioadd
[all...]
H A Drtc-s3c.c354 ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
385 tmp = readw(base + S3C2410_RTCCON);
399 if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
402 tmp = readw(base + S3C2410_RTCCON);
407 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
410 tmp = readw(base + S3C2410_RTCCON);
415 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
418 tmp = readw(base + S3C2410_RTCCON);
530 readw(s3c_rtc_base + S3C2410_RTCCON));
570 tmp = readw(s3c_rtc_bas
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/drivers/mmc/host/
H A Dimxmmc.c104 reg = readw(host->base + MMC_REG_STR_STP_CLK);
108 reg = readw(host->base + MMC_REG_STR_STP_CLK);
113 reg = readw(host->base + MMC_REG_STATUS);
116 reg = readw(host->base + MMC_REG_STATUS);
133 reg = readw(host->base + MMC_REG_STR_STP_CLK);
143 reg = readw(host->base + MMC_REG_STR_STP_CLK);
150 reg = readw(host->base + MMC_REG_STATUS);
153 reg = readw(host->base + MMC_REG_STATUS);
170 reg = readw(host->base + MMC_REG_STR_STP_CLK);
213 *pstat |= readw(hos
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H A Dsdhci-pxav3.c64 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
92 tmp = readw(host->ioaddr + SD_CE_ATA_2);
97 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
106 if ((readw(host->ioaddr + SD_CE_ATA_2)
116 tmp = readw(host->ioaddr + SD_CE_ATA_2);
H A Dsdhci-dove.c38 ret = readw(host->ioaddr + reg);
H A Dsdhci-pxav2.c64 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
76 tmp = readw(host->ioaddr + SD_FIFO_PARAM);
80 tmp = readw(host->ioaddr + SD_FIFO_PARAM);
94 tmp = readw(host->ioaddr + SD_CE_ATA_2);
/drivers/input/keyboard/
H A Dimx_keypad.c99 reg_val = readw(keypad->mmio_base + KPDR);
103 reg_val = readw(keypad->mmio_base + KPCR);
109 reg_val = readw(keypad->mmio_base + KPCR);
118 reg_val = readw(keypad->mmio_base + KPDR);
132 reg_val = readw(keypad->mmio_base + KPDR);
140 reg_val = readw(keypad->mmio_base + KPDR);
264 reg_val = readw(keypad->mmio_base + KPSR);
268 reg_val = readw(keypad->mmio_base + KPSR);
282 reg_val = readw(keypad->mmio_base + KPSR);
286 reg_val = readw(keypa
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/drivers/net/ethernet/dlink/
H A Ddl2k.c242 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
683 int_status = readw (ioaddr + IntStatus);
782 writew (readw (ioaddr + TxStartThresh) + 0x10,
789 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
809 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
824 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
1005 stat_reg = readw (ioaddr + FramesAbortXSColls);
1009 stat_reg = readw (ioaddr + CarrierSenseErrors);
1015 readw (ioaddr + BcstFramesXmtdOk);
1017 readw (ioadd
[all...]
/drivers/dma/ioat/
H A Ddca.c339 readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);
365 readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);
400 global_req_table = readw(iobase + dca_offset + IOAT_DCA_GREQID_OFFSET);
428 dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
448 csi_fsb_control = readw(ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);
454 pcie_control = readw(ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);
514 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
540 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
595 global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET);
631 dca_offset = readw(iobas
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/drivers/staging/comedi/drivers/
H A Dicp_multi.c285 readw(devpriv->io_addr + ICP_MULTI_ADC_CSR),
298 readw(devpriv->io_addr + ICP_MULTI_ADC_CSR));
305 readw(devpriv->io_addr + ICP_MULTI_ADC_CSR));
311 if (!(readw(devpriv->io_addr +
320 readw(devpriv->io_addr +
351 (readw(devpriv->io_addr + ICP_MULTI_AI) >> 4) & 0x0fff;
425 if (!(readw(devpriv->io_addr +
434 readw(devpriv->io_addr +
540 data[1] = readw(devpriv->io_addr + ICP_MULTI_DI);
580 data[1] = readw(devpri
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/drivers/net/ethernet/i825xx/
H A Dni52.c255 if (readw(&((addr)->cmd_status)) & STAT_COMPL)
639 if ((readw(&cfg_cmd->cmd_status) & (STAT_OK|STAT_COMPL)) !=
642 dev->name, readw(&cfg_cmd->cmd_status));
665 if ((readw(&ias_cmd->cmd_status) & (STAT_OK|STAT_COMPL)) !=
667 printk(KERN_ERR "%s (ni52): individual address setup command failed: %04x\n", dev->name, readw(&ias_cmd->cmd_status));
688 if (!(readw(&tdr_cmd->cmd_status) & STAT_COMPL))
693 result = readw(&tdr_cmd->status);
735 if ((readw(&mc_cmd->cmd_status) & (STAT_COMPL|STAT_OK))
960 rbd = make32(readw(&p->rfd_top->rbd_offset));
962 totlen = readw(
[all...]
/drivers/net/ethernet/intel/e1000/
H A De1000_osdep.h81 readw((a)->hw_addr + \
107 readw((a)->flash_address + reg))
/drivers/net/ethernet/packetengines/
H A Dhamachi.c749 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32,
751 readw(ioaddr + ANLinkPartnerAbility));
824 if ((readw(ioaddr + MII_Status) & 1) == 0)
829 if ((readw(ioaddr + MII_Status) & 1) == 0)
831 return readw(ioaddr + MII_Rd_Data);
842 if ((readw(ioaddr + MII_Status) & 1) == 0)
849 if ((readw(ioaddr + MII_Status) & 1) == 0)
893 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6;
987 dev->name, readw(ioaddr + RxStatus), readw(ioadd
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/drivers/tty/serial/
H A Damba-pl011.c188 status = readw(uap->port.membase + UART01x_FR);
193 ch = readw(uap->port.membase + UART01x_DR) |
621 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
958 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1110 uap->old_status = readw(uap->port.membase + UART01x_FR) &
1222 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1251 status = readw(uap->port.membase + UART011_MIS);
1276 status = readw(uap->port.membase + UART011_MIS);
1289 unsigned int status = readw(uap->port.membase + UART01x_FR);
1297 unsigned int status = readw(ua
[all...]
/drivers/ata/
H A Dsata_svw.c188 tf->device = readw(ioaddr->device_addr);
189 feature = readw(ioaddr->error_addr);
190 nsect = readw(ioaddr->nsect_addr);
191 lbal = readw(ioaddr->lbal_addr);
192 lbam = readw(ioaddr->lbam_addr);
193 lbah = readw(ioaddr->lbah_addr);
H A Dsata_vsc.c206 tf->device = readw(ioaddr->device_addr);
207 feature = readw(ioaddr->error_addr);
208 nsect = readw(ioaddr->nsect_addr);
209 lbal = readw(ioaddr->lbal_addr);
210 lbam = readw(ioaddr->lbam_addr);
211 lbah = readw(ioaddr->lbah_addr);
/drivers/mtd/onenand/
H A Donenand_sim.c81 (readw(this->base + ONENAND_REG_WP_STATUS))
281 die = readw(this->base + ONENAND_REG_START_ADDRESS2);
314 boundary[die] = readw(this->base + ONENAND_DATARAM);
389 block = (int) readw(this->base + ONENAND_REG_START_ADDRESS1);
398 page = (int) readw(this->base + ONENAND_REG_START_ADDRESS8);
400 bufferram = (int) readw(this->base + ONENAND_REG_START_BUFFER);

Completed in 678 milliseconds

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