Searched refs:reg_clear (Results 1 - 4 of 4) sorted by relevance

/drivers/media/video/
H A Dmt9t031.c113 static int reg_clear(struct i2c_client *client, const u8 reg, function
159 ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
167 reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
182 ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
294 ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 1);
491 data = reg_clear(client, MT9T031_READ_MODE_2, 0x8000);
499 data = reg_clear(client, MT9T031_READ_MODE_2, 0x4000);
724 return reg_clear(client, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000);
H A Dmt9v022.c153 static int reg_clear(struct i2c_client *client, const u8 reg, function
191 ret = reg_clear(client, MT9V022_BLACK_LEVEL_CALIB_CTRL, 1);
493 data = reg_clear(client, MT9V022_READ_MODE, 0x10);
501 data = reg_clear(client, MT9V022_READ_MODE, 0x20);
524 if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0)
546 data = reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x1);
H A Dmt9m111.c133 #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val)) macro
381 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
710 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
719 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
758 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
H A Dmt9m001.c132 static int reg_clear(struct i2c_client *client, const u8 reg, function
411 data = reg_clear(client, MT9M001_READ_OPTIONS2, 0x8000);

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