Searched refs:timing (Results 1 - 25 of 98) sorted by relevance

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/drivers/gpu/drm/exynos/
H A Dexynos_drm_connector.c50 struct fb_videomode *timing = &panel->timing; local
53 mode->clock = timing->pixclock / 1000;
54 mode->vrefresh = timing->refresh;
56 mode->hdisplay = timing->xres;
57 mode->hsync_start = mode->hdisplay + timing->right_margin;
58 mode->hsync_end = mode->hsync_start + timing->hsync_len;
59 mode->htotal = mode->hsync_end + timing->left_margin;
61 mode->vdisplay = timing->yres;
62 mode->vsync_start = mode->vdisplay + timing
77 convert_to_video_timing(struct fb_videomode *timing, struct drm_display_mode *mode) argument
185 struct fb_videomode timing; local
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H A Dexynos_drm_fimd.c113 static int fimd_check_timing(struct device *dev, void *timing) argument
197 struct fb_videomode *timing = &panel->timing; local
208 /* setup vertical timing values. */
209 val = VIDTCON0_VBPD(timing->upper_margin - 1) |
210 VIDTCON0_VFPD(timing->lower_margin - 1) |
211 VIDTCON0_VSPW(timing->vsync_len - 1);
214 /* setup horizontal timing values. */
215 val = VIDTCON1_HBPD(timing->left_margin - 1) |
216 VIDTCON1_HFPD(timing
689 fimd_calc_clkdiv(struct fimd_context *ctx, struct fb_videomode *timing) argument
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H A Dexynos_drm_hdmi.h46 int (*check_timing)(void *ctx, void *timing);
/drivers/ide/
H A Dtriflex.c41 u16 timing = 0; local
48 timing = 0x0103;
51 timing = 0x0203;
54 timing = 0x0808;
59 timing = 0x0f0f;
62 timing = 0x0202;
65 timing = 0x0204;
68 timing = 0x0404;
71 timing = 0x0508;
74 timing
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H A Damd74xx.c47 * amd_set_speed() writes timing values to the chipset registers
51 struct ide_timing *timing)
56 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
60 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
63 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
66 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
67 case ATA_UDMA4: t = timing
50 amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, struct ide_timing *timing) argument
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H A Dht6560b.c76 * Perhaps I should explain something about these timing values:
91 * You can obtain optimized timing values by running Holtek IDESETUP.COM
92 * for DOS. DOS drivers get their timing values from command line, where
120 u8 select, timing; local
125 timing = HT_TIMING(drive);
135 if (select != current_select || timing != current_timing) {
137 current_timing = timing;
144 * Set timing for this drive:
146 outb(timing, hwif->io_ports.device_addr);
149 printk("ht6560b: %s: select=%#x timing
285 u8 timing; local
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H A Dvia82cxxx.c117 * via_set_speed - write timing registers
120 * @timing: IDE timing data to use
122 * via_set_speed writes timing values to the chipset registers
125 static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) argument
134 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
139 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
142 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing
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/drivers/video/via/
H A Dvia_modesetting.c33 void via_set_primary_timing(const struct display_timing *timing) argument
37 raw.hor_total = timing->hor_total / 8 - 5;
38 raw.hor_addr = timing->hor_addr / 8 - 1;
39 raw.hor_blank_start = timing->hor_blank_start / 8 - 1;
40 raw.hor_blank_end = timing->hor_blank_end / 8 - 1;
41 raw.hor_sync_start = timing->hor_sync_start / 8;
42 raw.hor_sync_end = timing->hor_sync_end / 8;
43 raw.ver_total = timing->ver_total - 2;
44 raw.ver_addr = timing->ver_addr - 1;
45 raw.ver_blank_start = timing
91 via_set_secondary_timing(const struct display_timing *timing) argument
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H A Dvia_modesetting.h52 void via_set_primary_timing(const struct display_timing *timing);
53 void via_set_secondary_timing(const struct display_timing *timing);
/drivers/video/
H A Dgbefb.c40 struct gbe_timing_info timing; member in struct:gbefb_par
423 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) argument
429 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1);
431 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1);
439 timing->pll_m = 4;
440 timing->pll_n = 1;
441 timing->pll_p = 0;
468 struct gbe_timing_info *timing)
479 /* Determine valid resolution and timing
515 /* set video timing informatio
467 compute_gbe_timing(struct fb_var_screeninfo *var, struct gbe_timing_info *timing) argument
543 gbe_set_timing_info(struct gbe_timing_info *timing) argument
915 struct gbe_timing_info timing; local
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/drivers/ata/
H A Dpata_triflex.c75 * triflex_load_timing - timing configuration
89 u32 timing = 0; local
101 timing = 0x0103;break;
103 timing = 0x0203;break;
105 timing = 0x0808;break;
109 timing = 0x0F0F;break;
111 timing = 0x0202;break;
113 timing = 0x0204;break;
115 timing = 0x0404;break;
117 timing
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H A Dpata_cmd640.c54 struct cmd640_reg *timing = ap->private_data; local
68 /* The second channel has shared timings and the setup timing is
100 /* Load setup timing */
116 timing->reg58[adev->devno] = (t.active << 4) | t.recover;
134 struct cmd640_reg *timing = ap->private_data; local
136 if (ap->port_no != 0 && adev->devno != timing->last) {
137 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]);
138 timing->last = adev->devno;
154 struct cmd640_reg *timing; local
156 timing
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H A Dpata_cs5530.c69 /* Now load the right timing register */
77 * cs5530_set_dmamode - DMA timing setup
89 u32 tuning, timing = 0; local
97 timing = 0x00921250;break;
99 timing = 0x00911140;break;
101 timing = 0x00911030;break;
103 timing = 0x00077771;break;
105 timing = 0x00012121;break;
107 timing = 0x00002020;break;
112 timing |
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H A Dpata_sis.c315 t1 &= 0xC0C00FFF; /* Mask out timing */
342 u16 timing; local
347 pci_read_config_word(pdev, drive_pci, &timing);
350 /* bits 3-0 hold recovery timing bits 8-10 active timing and
352 timing &= ~0x870F;
353 timing |= mwdma_bits[speed];
357 timing &= ~0x6000;
358 timing |= udma_bits[speed];
360 pci_write_config_word(pdev, drive_pci, timing);
381 u16 timing; local
420 u8 timing; local
454 u8 timing; local
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H A Dpata_at32.c89 * Setup SMC for the given ATA timing.
96 struct smc_timing timing; local
101 memset(&timing, 0, sizeof(struct smc_timing));
104 timing.read_cycle = ata->cyc8b;
107 timing.nrd_setup = ata->setup;
108 timing.nrd_pulse = ata->act8b;
109 timing.nrd_recover = ata->rec8b;
111 /* Convert nanosecond timing to clock cycles */
112 smc_set_timing(smc, &timing);
152 struct ata_timing timing; local
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H A Dpata_sl82c105.c16 * timing parameters.
68 * sl82c105_configure_piomode - set chip PIO timing
73 * Called to do the PIO mode setup. Our timing registers are shared
85 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); local
87 pci_write_config_word(pdev, timing, pio_timing[pio]);
89 pci_read_config_word(pdev, timing, &dummy);
97 * Called to do the PIO mode setup. Our timing registers are shared
98 * but we want to set the PIO timing by default.
122 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); local
125 pci_write_config_word(pdev, timing, dma_timin
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H A Dpata_legacy.c99 unsigned long timing; member in struct:legacy_data
366 /* Get the timing data in cycles. For now play safe at 50Mhz */
400 /* Get the timing data in cycles. For now play safe at 50Mhz */
476 /* Get the timing data in cycles */
479 /* Setup timing is shared */
491 /* Select the right timing bank for write timing */
511 /* Ensure the timing register mode is right */
555 /* Get the timing data in cycles */
558 /* Setup timing i
656 u8 timing; local
792 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); local
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/drivers/media/video/
H A Dbt819.c75 struct timing { struct
85 static struct timing timing_data[] = {
190 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; local
193 (((timing->vdelay >> 8) & 0x03) << 6) |
194 (((timing->vactive >> 8) & 0x03) << 4) |
195 (((timing->hdelay >> 8) & 0x03) << 2) |
196 ((timing->hactive >> 8) & 0x03);
197 init[0x04 * 2 - 1] = timing->vdelay & 0xff;
198 init[0x05 * 2 - 1] = timing
251 struct timing *timing = NULL; local
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/drivers/char/
H A Dbfin-otp.c84 * bfin_otp_init_timing - setup OTP timing parameters
90 u32 tp1, tp2, tp3, timing; local
95 timing = tp1 | tp2 | tp3;
96 if (bfrom_OtpCommand(OTP_INIT, timing))
99 return timing;
107 static void bfin_otp_deinit_timing(u32 timing) argument
111 bfrom_OtpCommand(OTP_INIT, timing & ~(-1 << 15));
123 u32 timing, page, base_flags, flags, ret; local
137 timing = bfin_otp_init_timing();
138 if (timing
180 u32 timing; local
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/drivers/pcmcia/
H A Dsa11xx_base.c81 struct soc_pcmcia_timing timing; local
86 soc_common_pcmcia_get_timing(skt, &timing);
88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io);
89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem);
90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr);
147 struct soc_pcmcia_timing timing; local
152 soc_common_pcmcia_get_timing(skt, &timing);
154 p+=sprintf(p, "I/O : %u (%u)\n", timing.io,
157 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr,
160 p+=sprintf(p, "common : %u (%u)\n", timing
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/drivers/gpu/drm/nouveau/
H A Dnouveau_perf.c167 u8 *perf, *timing = NULL; local
184 timing = ROMPTR(dev, P.data[4]);
187 timing = ROMPTR(dev, P.data[8]);
190 if (timing && timing[0] == 0x10) {
192 if (ramcfg && ramcfg[1] < timing[2]) {
193 *ver = timing[0];
194 *len = timing[3];
195 return timing + timing[
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/drivers/mtd/nand/
H A Dcafe_nand.c90 static int timing[3]; variable
91 module_param_array(timing, int, &numtimings, 0644);
696 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
701 timing[0], timing[1], timing[2]);
703 timing[0] = cafe_readl(cafe, NAND_TIMING1);
704 timing[1] = cafe_readl(cafe, NAND_TIMING2);
705 timing[2] = cafe_readl(cafe, NAND_TIMING3);
707 if (timing[
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/drivers/media/video/omap3isp/
H A Dispcsi2.c341 * csi2_timing_config - CSI2 timing configuration.
342 * @timing: csi2_timing_cfg structure
346 struct isp_csi2_timing_cfg *timing)
352 if (timing->force_rx_mode)
353 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
355 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
357 if (timing->stop_state_16x)
358 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
360 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
362 if (timing
344 csi2_timing_config(struct isp_device *isp, struct isp_csi2_device *csi2, struct isp_csi2_timing_cfg *timing) argument
544 struct isp_csi2_timing_cfg *timing = &csi2->timing[0]; local
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/drivers/gpu/drm/
H A Ddrm_edid.c59 /* Detail timing is in cm not mm */
61 /* Detailed timing descriptors have bogus size values, so just take the
509 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
635 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
664 * @t: standard timing params
665 * @timing_level: standard timing level
667 * Take the standard timing params (in this case width, aspect, and refresh)
812 * drm_mode_detailed - create a new mode from an EDID detailed timing section
815 * @timing: EDID detailed timing inf
821 drm_mode_detailed(struct drm_device *dev, struct edid *edid, struct detailed_timing *timing, u32 quirks) argument
970 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, struct detailed_timing *timing) argument
1002 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, struct detailed_timing *timing) argument
1023 do_inferred_modes(struct detailed_timing *timing, void *c) argument
1050 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) argument
1079 do_established_modes(struct detailed_timing *timing, void *c) argument
1126 do_standard_modes(struct detailed_timing *timing, void *c) argument
1186 drm_cvt_modes(struct drm_connector *connector, struct detailed_timing *timing) argument
1236 do_cvt_mode(struct detailed_timing *timing, void *c) argument
1261 do_detailed_mode(struct detailed_timing *timing, void *c) argument
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/drivers/video/exynos/
H A Dexynos_mipi_dsi_common.c731 struct fb_videomode *timing; local
734 timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
741 timing->upper_margin,
742 timing->lower_margin);
744 timing->left_margin,
745 timing->right_margin);
747 timing->vsync_len,
748 timing->hsync_len);
752 exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
753 timing
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