Searched refs:train_set (Results 1 - 6 of 6) sorted by relevance

/drivers/gpu/drm/nouveau/
H A Dnouveau_encoder.h38 void (*train_set)(struct drm_device *, struct dcb_entry *, u8 pattern); member in struct:dp_train_func
H A Dnouveau_dp.c250 dp->func->train_set(dev, dp->dcb, pattern);
H A Dnv50_sor.c309 .train_set = nv50_sor_dp_train_set,
H A Dnvd0_display.c1371 .train_set = nvd0_sor_dp_train_set,
/drivers/gpu/drm/radeon/
H A Datombios_dp.c369 u8 train_set[4])
401 train_set[lane] = v | p;
673 u8 train_set[4]; member in struct:radeon_dp_link_train_info
684 0, dp_info->train_set[0]); /* sets all lanes at once */
688 dp_info->train_set, dp_info->dp_lane_count, 0);
804 memset(dp_info->train_set, 0, 4);
828 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
836 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
845 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
847 /* Compute new train_set a
367 dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], int lane_count, u8 train_set[4]) argument
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/drivers/gpu/drm/i915/
H A Dintel_dp.c61 uint8_t train_set[4]; member in struct:intel_dp
1496 intel_dp->train_set[lane] = v | p;
1500 intel_dp_signal_levels(uint8_t train_set) argument
1504 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1519 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1539 intel_gen6_edp_signal_levels(uint8_t train_set) argument
1541 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1567 intel_gen7_edp_signal_levels(uint8_t train_set) argument
1569 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1662 intel_dp->train_set,
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