Searched refs:write_reg (Results 1 - 25 of 80) sorted by relevance

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/drivers/staging/media/go7007/
H A Dwis-uda1342.c27 static int write_reg(struct i2c_client *client, int reg, int value) function
44 write_reg(client, 0x00, 0x1441); /* select input 2 */
47 write_reg(client, 0x00, 0x1241); /* select input 1 */
74 write_reg(client, 0x00, 0x8000); /* reset registers */
75 write_reg(client, 0x00, 0x1241); /* select input 1 */
H A Dwis-saa7113.c105 static int write_reg(struct i2c_client *client, u8 reg, u8 value) function
140 write_reg(client, 0x0e, 0x01);
141 write_reg(client, 0x10, 0x40);
143 write_reg(client, 0x0e, 0x01);
144 write_reg(client, 0x10, 0x48);
146 write_reg(client, 0x0e, 0x50);
147 write_reg(client, 0x10, 0x48);
207 write_reg(client, 0x0a, dec->brightness);
216 write_reg(client, 0x0b, dec->contrast);
225 write_reg(clien
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H A Dwis-tw9903.c87 static int write_reg(struct i2c_client *client, u8 reg, u8 value) function
210 write_reg(client, 0x10, dec->brightness);
219 write_reg(client, 0x11, dec->contrast);
229 /*write_reg(client, 0x0c, dec->saturation);*/
239 write_reg(client, 0x15, dec->hue);
H A Dwis-tw2804.c106 static int write_reg(struct i2c_client *client, u8 reg, u8 value, int channel) function
235 write_reg(client, 0x12, dec->brightness, dec->channel);
244 write_reg(client, 0x11, dec->contrast, dec->channel);
253 write_reg(client, 0x10, dec->saturation, dec->channel);
262 write_reg(client, 0x0f, dec->hue, dec->channel);
/drivers/media/video/ivtv/
H A Divtv-yuv.c179 write_reg(read_dec(i), 0x02804);
180 write_reg(read_dec(i), 0x0281c);
182 write_reg(read_dec(i), 0x02808);
183 write_reg(read_dec(i), 0x02820);
185 write_reg(read_dec(i), 0x0280c);
186 write_reg(read_dec(i), 0x02824);
188 write_reg(read_dec(i), 0x02810);
189 write_reg(read_dec(i), 0x02828);
191 write_reg(read_dec(i), 0x02814);
192 write_reg(read_de
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H A Divtv-firmware.c100 write_reg(IVTV_CMD_VDM_STOP, IVTV_REG_VDM);
103 write_reg(IVTV_CMD_AO_STOP, IVTV_REG_AO);
106 write_reg(IVTV_CMD_APU_PING, IVTV_REG_APU);
110 write_reg(IVTV_CMD_VPU_STOP16, IVTV_REG_VPU);
112 write_reg(IVTV_CMD_VPU_STOP15, IVTV_REG_VPU);
115 write_reg(IVTV_CMD_HW_BLOCKS_RST, IVTV_REG_HW_BLOCKS);
118 write_reg(IVTV_CMD_SPU_STOP, IVTV_REG_SPU);
123 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INIT, IVTV_REG_ENC_SDRAM_PRECHARGE);
126 write_reg(IVTV_CMD_SDRAM_REFRESH_INIT, IVTV_REG_ENC_SDRAM_REFRESH);
130 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INI
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H A Divtv-gpio.c116 write_reg(curdir, IVTV_REG_GPIO_DIR);
118 write_reg(curout, IVTV_REG_GPIO_OUT);
122 write_reg(curout, IVTV_REG_GPIO_OUT);
124 write_reg(curdir, IVTV_REG_GPIO_DIR);
139 write_reg(curout, IVTV_REG_GPIO_OUT);
143 write_reg(curout, IVTV_REG_GPIO_OUT);
177 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
218 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
230 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
256 write_reg((read_re
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/drivers/media/dvb/dvb-usb/
H A Dmxl111sf-demod.h29 int (*write_reg)(struct mxl111sf_state *state, u8 addr, u8 data); member in struct:mxl111sf_demod_config
H A Dmxl111sf-tuner.h54 int (*write_reg)(struct mxl111sf_state *state, u8 addr, u8 data); member in struct:mxl111sf_tuner_config
/drivers/net/can/sja1000/
H A Dsja1000.c90 * the write_reg() operation - especially on SMP systems.
93 priv->write_reg(priv, REG_CMR, val);
122 priv->write_reg(priv, REG_IER, IRQ_OFF);
131 priv->write_reg(priv, REG_MOD, MOD_RM); /* reset chip */
151 priv->write_reg(priv, REG_IER, IRQ_ALL);
153 priv->write_reg(priv, REG_IER,
159 priv->write_reg(priv, REG_MOD, 0x00);
176 priv->write_reg(priv, REG_TXERR, 0x0);
177 priv->write_reg(priv, REG_RXERR, 0x0);
219 priv->write_reg(pri
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H A Dsja1000_platform.c122 priv->write_reg = sp_write_reg32;
126 priv->write_reg = sp_write_reg16;
131 priv->write_reg = sp_write_reg8;
H A Dems_pci.c171 priv->write_reg(priv, REG_MOD, 1);
173 priv->write_reg(priv, REG_CDR, CDR_PELICAN);
314 priv->write_reg = ems_pci_v1_write_reg;
318 priv->write_reg = ems_pci_v2_write_reg;
/drivers/staging/media/cxd2099/
H A Dcxd2099.c228 static int write_reg(struct cxd *ci, u8 reg, u8 val) function
281 /* write_reg(ci, 0x0d, 0x00); */
282 /* write_reg(ci, 0x0e, 0x01); */
303 status = write_reg(ci, 0x00, 0x00);
306 status = write_reg(ci, 0x01, 0x00);
309 status = write_reg(ci, 0x02, 0x10);
312 status = write_reg(ci, 0x03, 0x00);
315 status = write_reg(ci, 0x05, 0xFF);
318 status = write_reg(ci, 0x06, 0x1F);
321 status = write_reg(c
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/drivers/net/ethernet/intel/igb/
H A De1000_phy.c117 if (!(hw->phy.ops.write_reg))
120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
124 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
465 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
533 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
561 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
646 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
730 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
750 ret_val = phy->ops.write_reg(hw,
762 ret_val = phy->ops.write_reg(h
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/drivers/ide/
H A Dopti621.c38 static void write_reg(u8 value, int reg) function
113 write_reg(drive->dn & 1, MISC_REG);
115 write_reg(tim, READ_REG);
117 write_reg(tim, WRITE_REG);
121 write_reg(0x85, CNTRL_REG);
125 write_reg(misc, MISC_REG);
/drivers/net/can/c_can/
H A Dc_can.c230 priv->write_reg(priv, &priv->regs->control, cntrl_save);
261 priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask,
263 priv->write_reg(priv, &priv->regs->ifregs[iface].com_req,
281 priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask,
283 priv->write_reg(priv, &priv->regs->ifregs[iface].com_req,
309 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1,
311 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, flags |
315 priv->write_reg(priv, &priv->regs->ifregs[iface].data[i / 2],
320 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
332 priv->write_reg(pri
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H A Dc_can.h73 void (*write_reg) (struct c_can_priv *priv, void *reg, u16 val); member in struct:c_can_priv
/drivers/rtc/
H A Drtc-r9701.c43 static int write_reg(struct device *dev, int address, unsigned char data) function
106 ret = write_reg(dev, RHRCNT, bin2bcd(dt->tm_hour));
107 ret = ret ? ret : write_reg(dev, RMINCNT, bin2bcd(dt->tm_min));
108 ret = ret ? ret : write_reg(dev, RSECCNT, bin2bcd(dt->tm_sec));
109 ret = ret ? ret : write_reg(dev, RDAYCNT, bin2bcd(dt->tm_mday));
110 ret = ret ? ret : write_reg(dev, RMONCNT, bin2bcd(dt->tm_mon + 1));
111 ret = ret ? ret : write_reg(dev, RYRCNT, bin2bcd(dt->tm_year - 100));
112 ret = ret ? ret : write_reg(dev, RWKCNT, 1 << dt->tm_wday);
/drivers/macintosh/
H A Dtherm_windtunnel.c120 write_reg( struct i2c_client *cl, int reg, int data, int len ) function
157 /* write_reg( x.fan, 0x24, val, 1 ); */
158 write_reg( x.fan, 0x25, val, 1 );
159 write_reg( x.fan, 0x20, 0, 1 );
224 if( write_reg( x.thermostat, 1, val, 1 ) )
228 write_reg( x.fan, 0x01, 0x01, 1 );
230 write_reg( x.fan, 0x23, 0x91, 1 );
232 write_reg( x.fan, 0x00, 0x95, 1 );
242 write_reg( x.thermostat, 2, x.overheat_hyst, 2 );
243 write_reg(
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/drivers/gpio/
H A Dgpio-generic.c138 bgc->write_reg(bgc->reg_dat, bgc->data);
150 bgc->write_reg(bgc->reg_set, mask);
152 bgc->write_reg(bgc->reg_clr, mask);
168 bgc->write_reg(bgc->reg_set, bgc->data);
194 bgc->write_reg(bgc->reg_dir, bgc->dir);
211 bgc->write_reg(bgc->reg_dir, bgc->dir);
226 bgc->write_reg(bgc->reg_dir, bgc->dir);
243 bgc->write_reg(bgc->reg_dir, bgc->dir);
258 bgc->write_reg = bgpio_write8;
262 bgc->write_reg
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H A Dgpio-it8761e.c53 static void write_reg(u8 data, u8 addr, u8 port) function
75 write_reg(0x2, 0x7, port);
105 write_reg(curr_dirs & ~(1 << bit), io_reg, port);
151 write_reg(curr_dirs | (1 << bit), io_reg, port);
/drivers/tty/
H A Dsynclinkmp.c623 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
1535 write_reg(info, CTL, RegValue);
2080 write_reg(info, IER2, 0);
2092 write_reg(info, (unsigned char)(timer + TMCS), 0);
2110 write_reg(info, SR1, status);
2113 write_reg(info, SR2, status2);
2236 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2237 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2238 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2241 write_reg(inf
5554 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value) function
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/drivers/video/mbx/
H A Dmbxfb.c39 #define write_reg(val, reg) do { writel((val), (reg)); } while(0) macro
449 write_reg(vsctrl, VSCTRL);
450 write_reg(vscadr, VSCADR);
451 write_reg(vubase, VUBASE);
452 write_reg(vvbase, VVBASE);
453 write_reg(vsadr, VSADR);
456 write_reg(sssize, SSSIZE);
457 write_reg(spoctrl, SPOCTRL);
458 write_reg(shctrl, SHCTRL);
466 write_reg(vovrcl
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/drivers/net/ethernet/realtek/
H A Datp.c274 write_reg(ioaddr, MODSEL, 0x00);
322 write_reg(ioaddr, CMR2, CMR2_NULL);
376 write_reg(ioaddr, CMR2, CMR2_EEPROM); /* Point to the EEPROM control registers. */
387 write_reg(ioaddr, CMR2, CMR2_NULL);
477 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
484 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
495 write_reg(ioaddr, TxCNT1, length >> 8);
496 write_reg(ioaddr, CMR1, CMR1_Xmit);
570 write_reg(ioaddr, IMR, 0);
585 write_reg(ioadd
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/drivers/isdn/hardware/mISDN/
H A Dhfcsusb.c90 static int write_reg(struct hfcsusb *hw, __u8 reg, __u8 val) function
202 write_reg(hw, HFCUSB_P_DATA, hw->led_state);
671 write_reg(hw, HFCUSB_STATES, 2 | HFCUSB_NT_G2_G3);
750 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 0 : 2);
751 write_reg(hw, HFCUSB_CON_HDLC, conhdlc);
752 write_reg(hw, HFCUSB_INC_RES_F, 2);
753 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 1 : 3);
754 write_reg(hw, HFCUSB_CON_HDLC, conhdlc);
755 write_reg(hw, HFCUSB_INC_RES_F, 2);
767 write_reg(h
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