| /drivers/media/video/ |
| H A D | omap24xxcam.c | 122 * Set xclk.
124 * To disable xclk, use value zero.
127 u32 xclk)
129 if (xclk) {
130 u32 divisor = CAM_MCLK / xclk;
830 * We have to adjust the xclk from OMAP 2 side to
833 if (p.u.bt656.clock_curr != cam->if_u.bt656.xclk) {
834 u32 xclk = p.u.bt656.clock_curr; local
837 if (xclk == 0)
840 if (xclk > CAM_MCL
126 omap24xxcam_core_xclk_set(const struct omap24xxcam_device *cam, u32 xclk) argument
[all...] |
| H A D | omap24xxcam.h | 484 u32 xclk; member in struct:omap24xxcam_device::__anon1628::parallel
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| /drivers/media/video/em28xx/ |
| H A D | em28xx-cards.c | 400 .xclk = EM28XX_XCLK_FREQUENCY_20MHZ,
435 .xclk = EM28XX_XCLK_FREQUENCY_48MHZ,
758 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ,
852 .xclk = EM28XX_XCLK_I2S_MSB_TIMING |
907 .xclk = EM28XX_XCLK_IR_RC5_MODE |
1151 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ, /* NEC IR */
1405 .xclk = EM28XX_XCLK_FREQUENCY_10MHZ,
1513 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ,
1642 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ, /* NEC IR */
1667 .xclk
[all...] |
| H A D | em28xx-input.c | 354 /* Adjust xclk based o IR table for RC5/NEC tables */
357 dev->board.xclk |= EM28XX_XCLK_IR_RC5_MODE;
360 dev->board.xclk &= ~EM28XX_XCLK_IR_RC5_MODE;
366 em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, dev->board.xclk,
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| H A D | em28xx-core.c | 425 u8 xclk; local
443 xclk = dev->board.xclk & 0x7f;
445 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
447 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
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| H A D | em28xx.h | 429 unsigned char xclk, i2c_speed; member in struct:em28xx_board
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| /drivers/video/aty/ |
| H A D | atyfb_base.c | 311 static int xclk; variable
372 int pll, mclk, xclk, ecp_max; member in struct:__anon5769
447 par->pll_limits.xclk = aty_chips[i].xclk;
475 par->pll_limits.xclk = 67;
483 par->pll_limits.xclk = 67;
493 par->pll_limits.xclk = 67;
501 par->pll_limits.xclk = 67;
513 par->pll_limits.xclk = 67;
521 par->pll_limits.xclk
2277 aty_calc_mem_refresh(struct atyfb_par *par, int xclk) argument
[all...] |
| H A D | aty128fb.c | 371 u32 xclk; member in struct:aty128_constants
876 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
880 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
882 par->constants.xclk, par->constants.ref_divider,
935 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
956 if (!par->constants.xclk)
957 par->constants.xclk = 0x1d4d; /* same as mclk */
1391 u32 xclk = par->constants.xclk; local
1400 n = xclk * fifo_widt
[all...] |
| H A D | atyfb.h | 49 int sclk, mclk, mclk_pm, xclk; member in struct:pll_info
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| /drivers/media/video/omap3isp/ |
| H A D | isp.h | 128 u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel);
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| H A D | isp.c | 183 * @xclk: Desired frequency of the clock in Hz. 0 = stable low, 1 is stable high
187 * (TCTRL_CTRL) to generate the desired xclk clock value.
189 * Divisor = cam_mclk_hz / xclk
193 static u32 isp_set_xclk(struct isp_device *isp, u32 xclk, u8 xclksel) argument
204 if (xclk >= mclk_hz) {
207 } else if (xclk >= 2) {
208 divisor = mclk_hz / xclk;
213 divisor = xclk;
236 "xclk. Must be 0 (A) or 1 (B).\n");
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| /drivers/media/video/cx231xx/ |
| H A D | cx231xx.h | 366 unsigned char xclk, i2c_speed; member in struct:cx231xx_board
|