Searched refs:val (Results 1 - 25 of 2595) sorted by relevance

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/drivers/net/wireless/brcm80211/brcmsmac/
H A Dtypes.h133 #define CONF_HAS(config, val) ((config) & (1 << (val)))
138 #define CONF_IS(config, val) ((config) == (1 << (val)))
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val))))
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
141 #define CONF_LT(config, val) ((config) & ((1 << (val))
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/drivers/staging/comedi/drivers/
H A Dam9513.h49 #define Am9513_write_register(reg, val) \
52 Am9513_output_data(val>>8); \
53 Am9513_output_data(val&0xff); \
56 #define Am9513_read_register(reg, val) \
59 val = Am9513_input_data()<<8; \
60 val |= Am9513_input_data(); \
65 #define Am9513_write_register(reg, val) \
68 Am9513_output_data(val); \
71 #define Am9513_read_register(reg, val) \
74 val
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/drivers/net/ethernet/neterion/vxge/
H A Dvxge-reg.h23 * vxge_vBIT(val, loc, sz) - set bits at offset
25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz)))
54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4)
55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4)
56 #define VXGE_EPROM_IMG_FIX(val) (u3
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/drivers/media/common/tuners/
H A Dtda18271-maps.c31 u8 val; member in struct:tda18271_map
202 { .rfmax = 62000, .val = 0x00 },
203 { .rfmax = 84000, .val = 0x01 },
204 { .rfmax = 100000, .val = 0x02 },
205 { .rfmax = 140000, .val = 0x03 },
206 { .rfmax = 170000, .val = 0x04 },
207 { .rfmax = 180000, .val = 0x05 },
208 { .rfmax = 865000, .val = 0x06 },
209 { .rfmax = 0, .val = 0x00 }, /* end */
213 { .rfmax = 61100, .val
936 int val, i = 0; local
1118 tda18271_lookup_map(struct dvb_frontend *fe, enum tda18271_map_type map_type, u32 *freq, u8 *val) argument
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/drivers/media/video/cx18/
H A Dcx18-io.c27 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) argument
30 u16 val2 = val | (val << 8);
35 cx18_writeb(cx, (u8) val, dst);
55 cx18_writeb(cx, (u8) val, dst);
58 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) argument
60 cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
61 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
65 cx18_sw1_irq_disable(struct cx18 *cx, u32 val) argument
71 cx18_sw2_irq_enable(struct cx18 *cx, u32 val) argument
78 cx18_sw2_irq_disable(struct cx18 *cx, u32 val) argument
84 cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val) argument
93 u32 val; local
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H A Dcx18-io.h44 void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) argument
46 __raw_writel(val, addr);
49 static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) argument
53 cx18_raw_writel_noretry(cx, val, addr);
54 if (val == cx18_raw_readl(cx, addr))
66 void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) argument
68 writel(val, addr);
71 static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) argument
75 cx18_writel_noretry(cx, val, addr);
76 if (val
82 cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, u32 eval, u32 mask) argument
104 cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) argument
109 cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr) argument
125 cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr) argument
130 cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr) argument
151 cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg) argument
156 cx18_write_reg(struct cx18 *cx, u32 val, u32 reg) argument
161 cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg, u32 eval, u32 mask) argument
174 cx18_write_enc(struct cx18 *cx, u32 val, u32 addr) argument
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/drivers/net/ethernet/chelsio/cxgb/
H A Dmy3126.c38 u32 val; local
46 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
47 val16 = (u16) val;
65 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val);
66 act_count += val;
69 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
70 cphy->elmer_gpo = val;
72 if ( (val & (1 << 8)) || (val & (1 << 19)) ||
75 val |
112 u32 val; local
188 u32 val; local
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H A Dmv88x201x.c122 u32 val; local
126 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
127 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
128 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
133 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
137 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
139 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
143 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
144 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
175 u32 val local
215 u32 val; local
239 u32 val; local
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/drivers/net/wimax/i2400m/
H A Dsysfs.c48 unsigned val; local
51 if (sscanf(buf, "%u\n", &val) != 1)
53 if (val != 0 && (val < 100 || val > 300000 || val % 100 != 0)) {
56 val);
59 result = i2400m_set_idle_timeout(i2400m, val);
/drivers/input/serio/
H A Di8042-ppcio.h35 static inline void i8042_write_data(int val) argument
37 writeb(val, kb_data);
40 static inline void i8042_write_command(int val) argument
42 writeb(val, kb_cs);
H A Di8042-jazzio.h41 static inline void i8042_write_data(int val) argument
43 jazz_kh->data = val;
46 static inline void i8042_write_command(int val) argument
48 jazz_kh->command = val;
H A Di8042-unicore32io.h49 static inline void i8042_write_data(int val) argument
51 writeb(val, I8042_DATA_REG);
54 static inline void i8042_write_command(int val) argument
56 writeb(val, I8042_COMMAND_REG);
/drivers/net/wireless/bcmdhd/include/
H A Dbcmendian.h36 #define BCMSWAP16(val) \
37 ((uint16)((((uint16)(val) & (uint16)0x00ffU) << 8) | \
38 (((uint16)(val) & (uint16)0xff00U) >> 8)))
41 #define BCMSWAP32(val) \
42 ((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \
43 (((uint32)(val) & (uint32)0x0000ff00U) << 8) | \
44 (((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \
45 (((uint32)(val) & (uint32)0xff000000U) >> 24)))
48 #define BCMSWAP32BY16(val) \
49 ((uint32)((((uint32)(val)
182 bcmswap16(uint16 val) argument
188 bcmswap32(uint32 val) argument
194 bcmswap32by16(uint32 val) argument
215 htol16_ua_store(uint16 val, uint8 *bytes) argument
223 htol32_ua_store(uint32 val, uint8 *bytes) argument
233 hton16_ua_store(uint16 val, uint8 *bytes) argument
241 hton32_ua_store(uint32 val, uint8 *bytes) argument
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/drivers/net/wireless/ath/ath5k/
H A Deeprom.c41 u16 val; local
48 val = (5 * bin) + 4800;
50 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
54 val = bin + 2300;
56 val = bin + 2400;
59 return val;
74 u16 val; local
94 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
95 if (val) {
96 eep_max = (val
117 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); local
192 u16 val; local
252 u16 val; local
515 u16 val; local
551 u16 val; local
797 u16 val; local
1022 u16 val; local
1285 u16 val; local
1474 u16 val; local
1604 u16 val; local
1707 u16 val; local
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/drivers/gpu/drm/nouveau/
H A Dnouveau_hwsq.h38 u32 val; member in struct:hwsq_ucode
46 hwsq->val = 0xffffffff;
72 hwsq_setf(struct hwsq_ucode *hwsq, u8 flag, int val) argument
75 if (val >= 0)
77 if (val >= 1)
91 hwsq_wr32(struct hwsq_ucode *hwsq, u32 reg, u32 val) argument
93 if (val != hwsq->val) {
94 if ((val & 0xffff0000) == (hwsq->val
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/drivers/mfd/
H A Dpcf50633-gpio.c38 int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val) argument
44 return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val);
50 u8 reg, val; local
53 val = pcf50633_reg_read(pcf, reg) & 0x07;
55 return val;
61 u8 val, reg; local
64 val = !!invert << 3;
66 return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val);
72 u8 reg, val; local
75 val
84 u8 reg, val, mask; local
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/drivers/hwmon/
H A Dhwmon-vid.c78 * val is the 4-bit or more VID code.
82 int vid_from_reg(int val, u8 vrm) argument
90 val &= 0x3f;
91 if ((val & 0x1f) == 0x1f)
93 if ((val & 0x1f) <= 0x09 || val == 0x0a)
94 vid = 1087500 - (val & 0x1f) * 25000;
96 vid = 1862500 - (val & 0x1f) * 25000;
97 if (val & 0x20)
103 val
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/drivers/media/video/bt8xx/
H A Dbttv-audio-hook.c78 unsigned int val, con; local
83 val = gpio_read();
96 if (con != (val & 0x300)) {
102 switch (val & 0x70) {
145 int val = 0; local
149 val = 0x02;
151 val = 0x01;
152 if (val) {
153 gpio_bits(0x03,val);
167 int val local
188 int val = 0; local
237 unsigned long val = 0; local
270 unsigned int val = 0; local
301 unsigned int val = 0xffff; local
331 unsigned long val = 0; local
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/drivers/infiniband/hw/mthca/
H A Dmthca_doorbell.h54 static inline void mthca_write64_raw(__be64 val, void __iomem *dest) argument
56 __raw_writeq((__force u64) val, dest);
65 static inline void mthca_write_db_rec(__be32 val[2], __be32 *db) argument
67 *(u64 *) db = *(u64 *) val;
82 static inline void mthca_write64_raw(__be64 val, void __iomem *dest) argument
84 __raw_writel(((__force u32 *) &val)[0], dest);
85 __raw_writel(((__force u32 *) &val)[1], dest + 4);
102 static inline void mthca_write_db_rec(__be32 val[2], __be32 *db) argument
104 db[0] = val[0];
106 db[1] = val[
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/drivers/staging/tidspbridge/dynload/
H A Dreloc.c86 * val Value to insert
101 int dload_repack(struct dload_state *dlthis, rvalue val, tgt_au_t * data, argument
111 objval = (val & mask);
137 unsigned tmp = (val >> fieldsz) + (sgn & 0x1);
168 rvalue val, reloc_amt, orig_val = 0; local
246 val = 0;
257 val = dlthis->relstk[dlthis->relstkidx];
300 val = dload_unpack(dlthis, data, fieldsz, offset,
304 orig_val = val;
307 val <<
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/drivers/staging/winbond/
H A Dphy_calibration.c47 u32 val; local
49 val = (data & 0x0FFF);
52 val |= 0xFFFFF000;
54 return (s32) val;
59 u32 val; local
66 val = data & 0x1FFF;
68 return val;
74 s32 val; local
76 val = (data & 0x0007);
79 val |
86 u32 val; local
101 s32 val; local
113 u32 val; local
128 s32 val; local
140 u32 val; local
155 s32 val; local
167 u32 val; local
321 u32 val; local
344 u32 val; local
445 u32 val; local
570 u32 val; local
696 u32 val; local
966 u32 val; local
1122 u32 val; local
1379 u32 val; local
1522 u32 val; local
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/drivers/scsi/pm8001/
H A Dpm8001_chips.h49 static inline void pm8001_write_32(void *addr, u32 offset, __le32 val) argument
51 *((__le32 *)(addr + offset)) = val;
61 u32 addr, u32 val)
63 writel(val, pm8001_ha->io_mem[bar].memvirtaddr + addr);
69 static inline void pm8001_mw32(void __iomem *addr, u32 offset, u32 val) argument
71 writel(val, addr + offset);
60 pm8001_cw32(struct pm8001_hba_info *pm8001_ha, u32 bar, u32 addr, u32 val) argument
/drivers/staging/sbe-2t3e3/
H A Dcpld.c43 u32 val; local
46 val = cpld_val_map[SBE_2T3E3_CPLD_VAL_LIU_FRAMER_RESET][sc->h.slot];
47 cpld_write(sc, SBE_2T3E3_CPLD_REG_STATIC_RESET, val);
49 val = 0;
50 cpld_write(sc, SBE_2T3E3_CPLD_REG_STATIC_RESET, val);
54 val = SBE_2T3E3_CPLD_VAL_CRC32 |
56 cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRA, val);
59 val = 0;
60 cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRB, val);
63 val
106 u32 val; local
123 u32 val; local
281 u32 val; local
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/drivers/media/dvb/frontends/
H A Dcx24110.h36 static inline int cx24110_pll_write(struct dvb_frontend *fe, u32 val) argument
39 (u8)((val >> 24) & 0xff),
40 (u8)((val >> 16) & 0xff),
41 (u8)((val >> 8) & 0xff)
/drivers/net/wireless/ath/ath9k/
H A Dar9003_rtt.c74 u32 val; local
76 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
77 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);
79 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
82 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
85 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
86 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
94 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
95 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
113 u32 val; local
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