1#ifndef __ALPHA_IO_H 2#define __ALPHA_IO_H 3 4#ifdef __KERNEL__ 5 6#include <linux/kernel.h> 7#include <linux/mm.h> 8#include <asm/compiler.h> 9#include <asm/pgtable.h> 10#include <asm/machvec.h> 11#include <asm/hwrpb.h> 12 13/* The generic header contains only prototypes. Including it ensures that 14 the implementation we have here matches that interface. */ 15#include <asm-generic/iomap.h> 16 17/* We don't use IO slowdowns on the Alpha, but.. */ 18#define __SLOW_DOWN_IO do { } while (0) 19#define SLOW_DOWN_IO do { } while (0) 20 21/* 22 * Virtual -> physical identity mapping starts at this offset 23 */ 24#ifdef USE_48_BIT_KSEG 25#define IDENT_ADDR 0xffff800000000000UL 26#else 27#define IDENT_ADDR 0xfffffc0000000000UL 28#endif 29 30/* 31 * We try to avoid hae updates (thus the cache), but when we 32 * do need to update the hae, we need to do it atomically, so 33 * that any interrupts wouldn't get confused with the hae 34 * register not being up-to-date with respect to the hardware 35 * value. 36 */ 37extern inline void __set_hae(unsigned long new_hae) 38{ 39 unsigned long flags = swpipl(IPL_MAX); 40 41 barrier(); 42 43 alpha_mv.hae_cache = new_hae; 44 *alpha_mv.hae_register = new_hae; 45 mb(); 46 /* Re-read to make sure it was written. */ 47 new_hae = *alpha_mv.hae_register; 48 49 setipl(flags); 50 barrier(); 51} 52 53extern inline void set_hae(unsigned long new_hae) 54{ 55 if (new_hae != alpha_mv.hae_cache) 56 __set_hae(new_hae); 57} 58 59/* 60 * Change virtual addresses to physical addresses and vv. 61 */ 62#ifdef USE_48_BIT_KSEG 63static inline unsigned long virt_to_phys(void *address) 64{ 65 return (unsigned long)address - IDENT_ADDR; 66} 67 68static inline void * phys_to_virt(unsigned long address) 69{ 70 return (void *) (address + IDENT_ADDR); 71} 72#else 73static inline unsigned long virt_to_phys(void *address) 74{ 75 unsigned long phys = (unsigned long)address; 76 77 /* Sign-extend from bit 41. */ 78 phys <<= (64 - 41); 79 phys = (long)phys >> (64 - 41); 80 81 /* Crop to the physical address width of the processor. */ 82 phys &= (1ul << hwrpb->pa_bits) - 1; 83 84 return phys; 85} 86 87static inline void * phys_to_virt(unsigned long address) 88{ 89 return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1))); 90} 91#endif 92 93#define page_to_phys(page) page_to_pa(page) 94 95static inline dma_addr_t __deprecated isa_page_to_bus(struct page *page) 96{ 97 return page_to_phys(page); 98} 99 100/* Maximum PIO space address supported? */ 101#define IO_SPACE_LIMIT 0xffff 102 103/* 104 * Change addresses as seen by the kernel (virtual) to addresses as 105 * seen by a device (bus), and vice versa. 106 * 107 * Note that this only works for a limited range of kernel addresses, 108 * and very well may not span all memory. Consider this interface 109 * deprecated in favour of the DMA-mapping API. 110 */ 111extern unsigned long __direct_map_base; 112extern unsigned long __direct_map_size; 113 114static inline unsigned long __deprecated virt_to_bus(void *address) 115{ 116 unsigned long phys = virt_to_phys(address); 117 unsigned long bus = phys + __direct_map_base; 118 return phys <= __direct_map_size ? bus : 0; 119} 120#define isa_virt_to_bus virt_to_bus 121 122static inline void * __deprecated bus_to_virt(unsigned long address) 123{ 124 void *virt; 125 126 /* This check is a sanity check but also ensures that bus address 0 127 maps to virtual address 0 which is useful to detect null pointers 128 (the NCR driver is much simpler if NULL pointers are preserved). */ 129 address -= __direct_map_base; 130 virt = phys_to_virt(address); 131 return (long)address <= 0 ? NULL : virt; 132} 133#define isa_bus_to_virt bus_to_virt 134 135/* 136 * There are different chipsets to interface the Alpha CPUs to the world. 137 */ 138 139#define IO_CONCAT(a,b) _IO_CONCAT(a,b) 140#define _IO_CONCAT(a,b) a ## _ ## b 141 142#ifdef CONFIG_ALPHA_GENERIC 143 144/* In a generic kernel, we always go through the machine vector. */ 145 146#define REMAP1(TYPE, NAME, QUAL) \ 147static inline TYPE generic_##NAME(QUAL void __iomem *addr) \ 148{ \ 149 return alpha_mv.mv_##NAME(addr); \ 150} 151 152#define REMAP2(TYPE, NAME, QUAL) \ 153static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \ 154{ \ 155 alpha_mv.mv_##NAME(b, addr); \ 156} 157 158REMAP1(unsigned int, ioread8, /**/) 159REMAP1(unsigned int, ioread16, /**/) 160REMAP1(unsigned int, ioread32, /**/) 161REMAP1(u8, readb, const volatile) 162REMAP1(u16, readw, const volatile) 163REMAP1(u32, readl, const volatile) 164REMAP1(u64, readq, const volatile) 165 166REMAP2(u8, iowrite8, /**/) 167REMAP2(u16, iowrite16, /**/) 168REMAP2(u32, iowrite32, /**/) 169REMAP2(u8, writeb, volatile) 170REMAP2(u16, writew, volatile) 171REMAP2(u32, writel, volatile) 172REMAP2(u64, writeq, volatile) 173 174#undef REMAP1 175#undef REMAP2 176 177extern inline void __iomem *generic_ioportmap(unsigned long a) 178{ 179 return alpha_mv.mv_ioportmap(a); 180} 181 182static inline void __iomem *generic_ioremap(unsigned long a, unsigned long s) 183{ 184 return alpha_mv.mv_ioremap(a, s); 185} 186 187static inline void generic_iounmap(volatile void __iomem *a) 188{ 189 return alpha_mv.mv_iounmap(a); 190} 191 192static inline int generic_is_ioaddr(unsigned long a) 193{ 194 return alpha_mv.mv_is_ioaddr(a); 195} 196 197static inline int generic_is_mmio(const volatile void __iomem *a) 198{ 199 return alpha_mv.mv_is_mmio(a); 200} 201 202#define __IO_PREFIX generic 203#define generic_trivial_rw_bw 0 204#define generic_trivial_rw_lq 0 205#define generic_trivial_io_bw 0 206#define generic_trivial_io_lq 0 207#define generic_trivial_iounmap 0 208 209#else 210 211#if defined(CONFIG_ALPHA_APECS) 212# include <asm/core_apecs.h> 213#elif defined(CONFIG_ALPHA_CIA) 214# include <asm/core_cia.h> 215#elif defined(CONFIG_ALPHA_IRONGATE) 216# include <asm/core_irongate.h> 217#elif defined(CONFIG_ALPHA_JENSEN) 218# include <asm/jensen.h> 219#elif defined(CONFIG_ALPHA_LCA) 220# include <asm/core_lca.h> 221#elif defined(CONFIG_ALPHA_MARVEL) 222# include <asm/core_marvel.h> 223#elif defined(CONFIG_ALPHA_MCPCIA) 224# include <asm/core_mcpcia.h> 225#elif defined(CONFIG_ALPHA_POLARIS) 226# include <asm/core_polaris.h> 227#elif defined(CONFIG_ALPHA_T2) 228# include <asm/core_t2.h> 229#elif defined(CONFIG_ALPHA_TSUNAMI) 230# include <asm/core_tsunami.h> 231#elif defined(CONFIG_ALPHA_TITAN) 232# include <asm/core_titan.h> 233#elif defined(CONFIG_ALPHA_WILDFIRE) 234# include <asm/core_wildfire.h> 235#else 236#error "What system is this?" 237#endif 238 239#endif /* GENERIC */ 240 241/* 242 * We always have external versions of these routines. 243 */ 244extern u8 inb(unsigned long port); 245extern u16 inw(unsigned long port); 246extern u32 inl(unsigned long port); 247extern void outb(u8 b, unsigned long port); 248extern void outw(u16 b, unsigned long port); 249extern void outl(u32 b, unsigned long port); 250 251extern u8 readb(const volatile void __iomem *addr); 252extern u16 readw(const volatile void __iomem *addr); 253extern u32 readl(const volatile void __iomem *addr); 254extern u64 readq(const volatile void __iomem *addr); 255extern void writeb(u8 b, volatile void __iomem *addr); 256extern void writew(u16 b, volatile void __iomem *addr); 257extern void writel(u32 b, volatile void __iomem *addr); 258extern void writeq(u64 b, volatile void __iomem *addr); 259 260extern u8 __raw_readb(const volatile void __iomem *addr); 261extern u16 __raw_readw(const volatile void __iomem *addr); 262extern u32 __raw_readl(const volatile void __iomem *addr); 263extern u64 __raw_readq(const volatile void __iomem *addr); 264extern void __raw_writeb(u8 b, volatile void __iomem *addr); 265extern void __raw_writew(u16 b, volatile void __iomem *addr); 266extern void __raw_writel(u32 b, volatile void __iomem *addr); 267extern void __raw_writeq(u64 b, volatile void __iomem *addr); 268 269/* 270 * Mapping from port numbers to __iomem space is pretty easy. 271 */ 272 273/* These two have to be extern inline because of the extern prototype from 274 <asm-generic/iomap.h>. It is not legal to mix "extern" and "static" for 275 the same declaration. */ 276extern inline void __iomem *ioport_map(unsigned long port, unsigned int size) 277{ 278 return IO_CONCAT(__IO_PREFIX,ioportmap) (port); 279} 280 281extern inline void ioport_unmap(void __iomem *addr) 282{ 283} 284 285static inline void __iomem *ioremap(unsigned long port, unsigned long size) 286{ 287 return IO_CONCAT(__IO_PREFIX,ioremap) (port, size); 288} 289 290static inline void __iomem *__ioremap(unsigned long port, unsigned long size, 291 unsigned long flags) 292{ 293 return ioremap(port, size); 294} 295 296static inline void __iomem * ioremap_nocache(unsigned long offset, 297 unsigned long size) 298{ 299 return ioremap(offset, size); 300} 301 302static inline void iounmap(volatile void __iomem *addr) 303{ 304 IO_CONCAT(__IO_PREFIX,iounmap)(addr); 305} 306 307static inline int __is_ioaddr(unsigned long addr) 308{ 309 return IO_CONCAT(__IO_PREFIX,is_ioaddr)(addr); 310} 311#define __is_ioaddr(a) __is_ioaddr((unsigned long)(a)) 312 313static inline int __is_mmio(const volatile void __iomem *addr) 314{ 315 return IO_CONCAT(__IO_PREFIX,is_mmio)(addr); 316} 317 318 319/* 320 * If the actual I/O bits are sufficiently trivial, then expand inline. 321 */ 322 323#if IO_CONCAT(__IO_PREFIX,trivial_io_bw) 324extern inline unsigned int ioread8(void __iomem *addr) 325{ 326 unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread8)(addr); 327 mb(); 328 return ret; 329} 330 331extern inline unsigned int ioread16(void __iomem *addr) 332{ 333 unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread16)(addr); 334 mb(); 335 return ret; 336} 337 338extern inline void iowrite8(u8 b, void __iomem *addr) 339{ 340 IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr); 341 mb(); 342} 343 344extern inline void iowrite16(u16 b, void __iomem *addr) 345{ 346 IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr); 347 mb(); 348} 349 350extern inline u8 inb(unsigned long port) 351{ 352 return ioread8(ioport_map(port, 1)); 353} 354 355extern inline u16 inw(unsigned long port) 356{ 357 return ioread16(ioport_map(port, 2)); 358} 359 360extern inline void outb(u8 b, unsigned long port) 361{ 362 iowrite8(b, ioport_map(port, 1)); 363} 364 365extern inline void outw(u16 b, unsigned long port) 366{ 367 iowrite16(b, ioport_map(port, 2)); 368} 369#endif 370 371#if IO_CONCAT(__IO_PREFIX,trivial_io_lq) 372extern inline unsigned int ioread32(void __iomem *addr) 373{ 374 unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread32)(addr); 375 mb(); 376 return ret; 377} 378 379extern inline void iowrite32(u32 b, void __iomem *addr) 380{ 381 IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr); 382 mb(); 383} 384 385extern inline u32 inl(unsigned long port) 386{ 387 return ioread32(ioport_map(port, 4)); 388} 389 390extern inline void outl(u32 b, unsigned long port) 391{ 392 iowrite32(b, ioport_map(port, 4)); 393} 394#endif 395 396#if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1 397extern inline u8 __raw_readb(const volatile void __iomem *addr) 398{ 399 return IO_CONCAT(__IO_PREFIX,readb)(addr); 400} 401 402extern inline u16 __raw_readw(const volatile void __iomem *addr) 403{ 404 return IO_CONCAT(__IO_PREFIX,readw)(addr); 405} 406 407extern inline void __raw_writeb(u8 b, volatile void __iomem *addr) 408{ 409 IO_CONCAT(__IO_PREFIX,writeb)(b, addr); 410} 411 412extern inline void __raw_writew(u16 b, volatile void __iomem *addr) 413{ 414 IO_CONCAT(__IO_PREFIX,writew)(b, addr); 415} 416 417extern inline u8 readb(const volatile void __iomem *addr) 418{ 419 u8 ret = __raw_readb(addr); 420 mb(); 421 return ret; 422} 423 424extern inline u16 readw(const volatile void __iomem *addr) 425{ 426 u16 ret = __raw_readw(addr); 427 mb(); 428 return ret; 429} 430 431extern inline void writeb(u8 b, volatile void __iomem *addr) 432{ 433 __raw_writeb(b, addr); 434 mb(); 435} 436 437extern inline void writew(u16 b, volatile void __iomem *addr) 438{ 439 __raw_writew(b, addr); 440 mb(); 441} 442#endif 443 444#if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1 445extern inline u32 __raw_readl(const volatile void __iomem *addr) 446{ 447 return IO_CONCAT(__IO_PREFIX,readl)(addr); 448} 449 450extern inline u64 __raw_readq(const volatile void __iomem *addr) 451{ 452 return IO_CONCAT(__IO_PREFIX,readq)(addr); 453} 454 455extern inline void __raw_writel(u32 b, volatile void __iomem *addr) 456{ 457 IO_CONCAT(__IO_PREFIX,writel)(b, addr); 458} 459 460extern inline void __raw_writeq(u64 b, volatile void __iomem *addr) 461{ 462 IO_CONCAT(__IO_PREFIX,writeq)(b, addr); 463} 464 465extern inline u32 readl(const volatile void __iomem *addr) 466{ 467 u32 ret = __raw_readl(addr); 468 mb(); 469 return ret; 470} 471 472extern inline u64 readq(const volatile void __iomem *addr) 473{ 474 u64 ret = __raw_readq(addr); 475 mb(); 476 return ret; 477} 478 479extern inline void writel(u32 b, volatile void __iomem *addr) 480{ 481 __raw_writel(b, addr); 482 mb(); 483} 484 485extern inline void writeq(u64 b, volatile void __iomem *addr) 486{ 487 __raw_writeq(b, addr); 488 mb(); 489} 490#endif 491 492#define inb_p inb 493#define inw_p inw 494#define inl_p inl 495#define outb_p outb 496#define outw_p outw 497#define outl_p outl 498#define readb_relaxed(addr) __raw_readb(addr) 499#define readw_relaxed(addr) __raw_readw(addr) 500#define readl_relaxed(addr) __raw_readl(addr) 501#define readq_relaxed(addr) __raw_readq(addr) 502 503#define mmiowb() 504 505/* 506 * String version of IO memory access ops: 507 */ 508extern void memcpy_fromio(void *, const volatile void __iomem *, long); 509extern void memcpy_toio(volatile void __iomem *, const void *, long); 510extern void _memset_c_io(volatile void __iomem *, unsigned long, long); 511 512static inline void memset_io(volatile void __iomem *addr, u8 c, long len) 513{ 514 _memset_c_io(addr, 0x0101010101010101UL * c, len); 515} 516 517#define __HAVE_ARCH_MEMSETW_IO 518static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len) 519{ 520 _memset_c_io(addr, 0x0001000100010001UL * c, len); 521} 522 523/* 524 * String versions of in/out ops: 525 */ 526extern void insb (unsigned long port, void *dst, unsigned long count); 527extern void insw (unsigned long port, void *dst, unsigned long count); 528extern void insl (unsigned long port, void *dst, unsigned long count); 529extern void outsb (unsigned long port, const void *src, unsigned long count); 530extern void outsw (unsigned long port, const void *src, unsigned long count); 531extern void outsl (unsigned long port, const void *src, unsigned long count); 532 533/* 534 * The Alpha Jensen hardware for some rather strange reason puts 535 * the RTC clock at 0x170 instead of 0x70. Probably due to some 536 * misguided idea about using 0x70 for NMI stuff. 537 * 538 * These defines will override the defaults when doing RTC queries 539 */ 540 541#ifdef CONFIG_ALPHA_GENERIC 542# define RTC_PORT(x) ((x) + alpha_mv.rtc_port) 543#else 544# ifdef CONFIG_ALPHA_JENSEN 545# define RTC_PORT(x) (0x170+(x)) 546# else 547# define RTC_PORT(x) (0x70 + (x)) 548# endif 549#endif 550#define RTC_ALWAYS_BCD 0 551 552/* 553 * Some mucking forons use if[n]def writeq to check if platform has it. 554 * It's a bloody bad idea and we probably want ARCH_HAS_WRITEQ for them 555 * to play with; for now just use cpp anti-recursion logics and make sure 556 * that damn thing is defined and expands to itself. 557 */ 558 559#define writeq writeq 560#define readq readq 561 562/* 563 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 564 * access 565 */ 566#define xlate_dev_mem_ptr(p) __va(p) 567 568/* 569 * Convert a virtual cached pointer to an uncached pointer 570 */ 571#define xlate_dev_kmem_ptr(p) p 572 573#endif /* __KERNEL__ */ 574 575#endif /* __ALPHA_IO_H */ 576