1dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas/* 2dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * arch/arm/include/asm/pgtable-3level.h 3dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * 4dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * Copyright (C) 2011 ARM Ltd. 5dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * Author: Catalin Marinas <catalin.marinas@arm.com> 6dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * 7dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * This program is free software; you can redistribute it and/or modify 8dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * it under the terms of the GNU General Public License version 2 as 9dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * published by the Free Software Foundation. 10dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * 11dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * This program is distributed in the hope that it will be useful, 12dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 13dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * GNU General Public License for more details. 15dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * 16dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * You should have received a copy of the GNU General Public License 17dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * along with this program; if not, write to the Free Software 18dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas */ 20dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#ifndef _ASM_PGTABLE_3LEVEL_H 21dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define _ASM_PGTABLE_3LEVEL_H 22dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 23dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas/* 24dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * With LPAE, there are 3 levels of page tables. Each level has 512 entries of 25dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * 8 bytes each, occupying a 4K page. The first level table covers a range of 26dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * 512GB, each entry representing 1GB. Since we are limited to 4GB input 27dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * address range, only 4 entries in the PGD are used. 28dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * 29dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * There are enough spare bits in a page table entry for the kernel specific 30dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * state. 31dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas */ 32dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PTRS_PER_PTE 512 33dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PTRS_PER_PMD 512 34dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PTRS_PER_PGD 4 35dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 36dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) 37dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PTE_HWTABLE_OFF (0) 38dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) 39dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 40dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas/* 41dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * PGDIR_SHIFT determines the size a top-level page table entry can map. 42dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas */ 43dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PGDIR_SHIFT 30 44dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 45dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas/* 46dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * PMD_SHIFT determines the size a middle-level page table entry can map. 47dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas */ 48dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PMD_SHIFT 21 49dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 50dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PMD_SIZE (1UL << PMD_SHIFT) 51dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PMD_MASK (~(PMD_SIZE-1)) 52dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 53dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define PGDIR_MASK (~(PGDIR_SIZE-1)) 54dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 55dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas/* 56dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * section address mask and size definitions. 57dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas */ 58dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define SECTION_SHIFT 21 59dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define SECTION_SIZE (1UL << SECTION_SHIFT) 60dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define SECTION_MASK (~(SECTION_SIZE-1)) 61dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 62dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE) 63dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 64dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas/* 65dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * "Linux" PTE definitions for LPAE. 66dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * 67dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * These bits overlap with the hardware bits but the naming is preserved for 68dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * consistency with the classic page table format. 69dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas */ 70dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Valid */ 71dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ 72dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ 73dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ 74dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 75dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 76dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 77dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ 78dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ 79dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) /* unused */ 80dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */ 81dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 82dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas/* 83dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * To be used in assembly code with the upper page attributes. 84dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas */ 85dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_XN_HIGH (1 << (54 - 32)) 86dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_DIRTY_HIGH (1 << (55 - 32)) 87dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 88dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas/* 89dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 90dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas */ 91dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ 92dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 93dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */ 94dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 95dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */ 96dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */ 97dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */ 98dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 99dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 100dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2) 101dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas 102da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas/* 103da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas * Software PGD flags. 104da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas */ 105da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */ 106da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 107da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#ifndef __ASSEMBLY__ 108da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 109da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define pud_none(pud) (!pud_val(pud)) 110da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define pud_bad(pud) (!(pud_val(pud) & 2)) 111da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define pud_present(pud) (pud_val(pud)) 112da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 113da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define pud_clear(pudp) \ 114da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas do { \ 115da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas *pudp = __pud(0); \ 116da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas clean_pmd_entry(pudp); \ 117da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas } while (0) 118da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 119da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define set_pud(pudp, pud) \ 120da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas do { \ 121da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas *pudp = pud; \ 122da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas flush_pmd_entry(pudp); \ 123da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas } while (0) 124da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 125da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinasstatic inline pmd_t *pud_page_vaddr(pud_t pud) 126da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas{ 127da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); 128da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas} 129da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 130da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas/* Find an entry in the second-level page table.. */ 131da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 132da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinasstatic inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) 133da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas{ 134da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); 135da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas} 136da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 137da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) 138da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 139da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define copy_pmd(pmdpd,pmdps) \ 140da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas do { \ 141da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas *pmdpd = *pmdps; \ 142da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas flush_pmd_entry(pmdpd); \ 143da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas } while (0) 144da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 145da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define pmd_clear(pmdp) \ 146da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas do { \ 147da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas *pmdp = __pmd(0); \ 148da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas clean_pmd_entry(pmdp); \ 149da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas } while (0) 150da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 151da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext))) 152da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 153da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas#endif /* __ASSEMBLY__ */ 154da02877987e6e173ebba137d4e1e155e1f1151cdCatalin Marinas 155dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89Catalin Marinas#endif /* _ASM_PGTABLE_3LEVEL_H */ 156