11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 24baa9922430662431231ac637adedddbb0cfb2d7Russell King * arch/arm/include/asm/ptrace.h 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 1996-2003 Russell King 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License version 2 as 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef __ASM_ARM_PTRACE_H 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define __ASM_ARM_PTRACE_H 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13d1cbbd6b413510c6512f4f80ffd48db1a8dd554aCatalin Marinas#include <asm/hwcap.h> 14d1cbbd6b413510c6512f4f80ffd48db1a8dd554aCatalin Marinas 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTRACE_GETREGS 12 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTRACE_SETREGS 13 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTRACE_GETFPREGS 14 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTRACE_SETFPREGS 15 191b11652286a06988f721b506b094d026e8892e2cRussell King/* PTRACE_ATTACH is 16 */ 201b11652286a06988f721b506b094d026e8892e2cRussell King/* PTRACE_DETACH is 17 */ 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTRACE_GETWMMXREGS 18 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTRACE_SETWMMXREGS 19 231b11652286a06988f721b506b094d026e8892e2cRussell King/* 20 is unused */ 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTRACE_OLDSETOPTIONS 21 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTRACE_GET_THREAD_AREA 22 263f471126ee53feb5e9b210ea2f525ed3bb9b7a7fNicolas Pitre#define PTRACE_SET_SYSCALL 23 275429b060df6d556f396b78364ad017686015bc34Lennert Buytenhek/* PTRACE_SYSCALL is 24 */ 285429b060df6d556f396b78364ad017686015bc34Lennert Buytenhek#define PTRACE_GETCRUNCHREGS 25 295429b060df6d556f396b78364ad017686015bc34Lennert Buytenhek#define PTRACE_SETCRUNCHREGS 26 303d1228ead618b88e8606015cbabc49019981805dCatalin Marinas#define PTRACE_GETVFPREGS 27 313d1228ead618b88e8606015cbabc49019981805dCatalin Marinas#define PTRACE_SETVFPREGS 28 32864232fa1a2f8dfe003438ef0851a56722740f3eWill Deacon#define PTRACE_GETHBPREGS 29 33864232fa1a2f8dfe003438ef0851a56722740f3eWill Deacon#define PTRACE_SETHBPREGS 30 345429b060df6d556f396b78364ad017686015bc34Lennert Buytenhek 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PSR bits 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define USR26_MODE 0x00000000 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIQ26_MODE 0x00000001 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ26_MODE 0x00000002 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SVC26_MODE 0x00000003 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define USR_MODE 0x00000010 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIQ_MODE 0x00000011 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_MODE 0x00000012 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SVC_MODE 0x00000013 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ABT_MODE 0x00000017 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define UND_MODE 0x0000001b 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SYSTEM_MODE 0x0000001f 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MODE32_BIT 0x00000010 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MODE_MASK 0x0000001f 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_T_BIT 0x00000020 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_F_BIT 0x00000040 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_I_BIT 0x00000080 54d1cbbd6b413510c6512f4f80ffd48db1a8dd554aCatalin Marinas#define PSR_A_BIT 0x00000100 5526584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#define PSR_E_BIT 0x00000200 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_J_BIT 0x01000000 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_Q_BIT 0x08000000 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_V_BIT 0x10000000 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_C_BIT 0x20000000 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_Z_BIT 0x40000000 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_N_BIT 0x80000000 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Groups of PSR bits 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_f 0xff000000 /* Flags */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_s 0x00ff0000 /* Status */ 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_x 0x0000ff00 /* Extension */ 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PSR_c 0x000000ff /* Control */ 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 71d71e1352e240dea32d481ad8d662e8de4406ac7eCatalin Marinas/* 727460bce42323df6570c7ba5091cb5201c7af1944Jon Medhurst * ARMv7 groups of PSR bits 73d71e1352e240dea32d481ad8d662e8de4406ac7eCatalin Marinas */ 747460bce42323df6570c7ba5091cb5201c7af1944Jon Medhurst#define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */ 75d71e1352e240dea32d481ad8d662e8de4406ac7eCatalin Marinas#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ 76d71e1352e240dea32d481ad8d662e8de4406ac7eCatalin Marinas#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 77d71e1352e240dea32d481ad8d662e8de4406ac7eCatalin Marinas#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ 78d71e1352e240dea32d481ad8d662e8de4406ac7eCatalin Marinas 7926584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas/* 8026584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas * Default endianness state 8126584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas */ 8226584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#ifdef CONFIG_CPU_ENDIAN_BE8 8326584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#define PSR_ENDSTATE PSR_E_BIT 8426584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#else 8526584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#define PSR_ENDSTATE 0 8626584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#endif 8726584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas 8868b7f7153fa58df710924fbb79722717d2d16094Paul Brook/* 8968b7f7153fa58df710924fbb79722717d2d16094Paul Brook * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 9068b7f7153fa58df710924fbb79722717d2d16094Paul Brook * process is located in memory. 9168b7f7153fa58df710924fbb79722717d2d16094Paul Brook */ 9268b7f7153fa58df710924fbb79722717d2d16094Paul Brook#define PT_TEXT_ADDR 0x10000 9368b7f7153fa58df710924fbb79722717d2d16094Paul Brook#define PT_DATA_ADDR 0x10004 9468b7f7153fa58df710924fbb79722717d2d16094Paul Brook#define PT_TEXT_END_ADDR 0x10008 9568b7f7153fa58df710924fbb79722717d2d16094Paul Brook 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef __ASSEMBLY__ 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 982dede2d8e925f4c2cb4e136b14df127685e15dd3Nicolas Pitre/* 992dede2d8e925f4c2cb4e136b14df127685e15dd3Nicolas Pitre * This struct defines the way the registers are stored on the 1002dede2d8e925f4c2cb4e136b14df127685e15dd3Nicolas Pitre * stack during a system call. Note that sizeof(struct pt_regs) 1012dede2d8e925f4c2cb4e136b14df127685e15dd3Nicolas Pitre * has to be a multiple of 8. 1022dede2d8e925f4c2cb4e136b14df127685e15dd3Nicolas Pitre */ 103092a4e957a835cbf6b2ec82a6a4d6ff06c0a362eJamie Iles#ifndef __KERNEL__ 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct pt_regs { 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds long uregs[18]; 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 107092a4e957a835cbf6b2ec82a6a4d6ff06c0a362eJamie Iles#else /* __KERNEL__ */ 108092a4e957a835cbf6b2ec82a6a4d6ff06c0a362eJamie Ilesstruct pt_regs { 109092a4e957a835cbf6b2ec82a6a4d6ff06c0a362eJamie Iles unsigned long uregs[18]; 110092a4e957a835cbf6b2ec82a6a4d6ff06c0a362eJamie Iles}; 111092a4e957a835cbf6b2ec82a6a4d6ff06c0a362eJamie Iles#endif /* __KERNEL__ */ 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_cpsr uregs[16] 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_pc uregs[15] 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_lr uregs[14] 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_sp uregs[13] 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_ip uregs[12] 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_fp uregs[11] 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r10 uregs[10] 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r9 uregs[9] 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r8 uregs[8] 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r7 uregs[7] 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r6 uregs[6] 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r5 uregs[5] 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r4 uregs[4] 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r3 uregs[3] 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r2 uregs[2] 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r1 uregs[1] 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_r0 uregs[0] 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ARM_ORIG_r0 uregs[17] 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1325be6f62b0059a3344437b4c2877152c58cb3fdebDave Martin/* 1335be6f62b0059a3344437b4c2877152c58cb3fdebDave Martin * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS 1345be6f62b0059a3344437b4c2877152c58cb3fdebDave Martin * and core dumps. 1355be6f62b0059a3344437b4c2877152c58cb3fdebDave Martin */ 1365be6f62b0059a3344437b4c2877152c58cb3fdebDave Martin#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ ) 1375be6f62b0059a3344437b4c2877152c58cb3fdebDave Martin 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef __KERNEL__ 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define user_mode(regs) \ 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (((regs)->ARM_cpsr & 0xf) == 0) 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ARM_THUMB 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define thumb_mode(regs) \ 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (((regs)->ARM_cpsr & PSR_T_BIT)) 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define thumb_mode(regs) (0) 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 150909d6c6c80311f800aee338e5fa528818b115951George G. Davis#define isa_mode(regs) \ 151909d6c6c80311f800aee338e5fa528818b115951George G. Davis ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ 152909d6c6c80311f800aee338e5fa528818b115951George G. Davis (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) 153909d6c6c80311f800aee338e5fa528818b115951George G. Davis 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define processor_mode(regs) \ 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ((regs)->ARM_cpsr & MODE_MASK) 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define interrupts_enabled(regs) \ 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (!((regs)->ARM_cpsr & PSR_I_BIT)) 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define fast_interrupts_enabled(regs) \ 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (!((regs)->ARM_cpsr & PSR_F_BIT)) 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Are the current registers suitable for user mode? 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (used to maintain security in signal handlers) 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline int valid_user_regs(struct pt_regs *regs) 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 16841e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King unsigned long mode = regs->ARM_cpsr & MODE_MASK; 16941e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King 17041e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King /* 17141e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King * Always clear the F (FIQ) and A (delayed abort) bits 17241e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King */ 17341e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); 17441e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King 17541e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { 17641e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King if (mode == USR_MODE) 17741e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King return 1; 17841e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE) 17941e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King return 1; 180d1cbbd6b413510c6512f4f80ffd48db1a8dd554aCatalin Marinas } 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Force CPSR to something logical... 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 18541e2e8fd34fff909a0e40129f6ac4233ecfa67a9Russell King regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; 186d1cbbd6b413510c6512f4f80ffd48db1a8dd554aCatalin Marinas if (!(elf_hwcap & HWCAP_26BIT)) 187d1cbbd6b413510c6512f4f80ffd48db1a8dd554aCatalin Marinas regs->ARM_cpsr |= USR_MODE; 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19229ef73b7a823b77a7cd0bdd7d7cded3fb6c2587bNathaniel Hustedstatic inline long regs_return_value(struct pt_regs *regs) 19329ef73b7a823b77a7cd0bdd7d7cded3fb6c2587bNathaniel Husted{ 19429ef73b7a823b77a7cd0bdd7d7cded3fb6c2587bNathaniel Husted return regs->ARM_r0; 19529ef73b7a823b77a7cd0bdd7d7cded3fb6c2587bNathaniel Husted} 19629ef73b7a823b77a7cd0bdd7d7cded3fb6c2587bNathaniel Husted 1971de765c1e940e23d83ec57035769e8af003f8796Russell King#define instruction_pointer(regs) (regs)->ARM_pc 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_SMP 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern unsigned long profile_pc(struct pt_regs *regs); 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define profile_pc(regs) instruction_pointer(regs) 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 205652a12ef98d16ccd1ee5cdf2c832ce5411ed3262Russell King#define predicate(x) ((x) & 0xf0000000) 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PREDICATE_ALWAYS 0xe0000000 207f22ab814a24e654b1de24db0c5f8b57b5ab2026aAdrian Bunk 208e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon/* 209592201a9f154cdd5db59304d1369e94d8b551803Jon Medhurst * True if instr is a 32-bit thumb instruction. This works if instr 210592201a9f154cdd5db59304d1369e94d8b551803Jon Medhurst * is the first or only half-word of a thumb instruction. It also works 211592201a9f154cdd5db59304d1369e94d8b551803Jon Medhurst * when instr holds all 32-bits of a wide thumb instruction if stored 212592201a9f154cdd5db59304d1369e94d8b551803Jon Medhurst * in the form (first_half<<16)|(second_half) 213592201a9f154cdd5db59304d1369e94d8b551803Jon Medhurst */ 214592201a9f154cdd5db59304d1369e94d8b551803Jon Medhurst#define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800) 215592201a9f154cdd5db59304d1369e94d8b551803Jon Medhurst 216592201a9f154cdd5db59304d1369e94d8b551803Jon Medhurst/* 217e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon * kprobe-based event tracer support 218e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon */ 219e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon#include <linux/stddef.h> 220e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon#include <linux/types.h> 221e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0)) 222e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon 223e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deaconextern int regs_query_register_offset(const char *name); 224e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deaconextern const char *regs_query_register_name(unsigned int offset); 225e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deaconextern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr); 226e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deaconextern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, 227e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon unsigned int n); 228e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon 229e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon/** 230e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon * regs_get_register() - get register value from its offset 231e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon * @regs: pt_regs from which register value is gotten 232e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon * @offset: offset number of the register. 233e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon * 234e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon * regs_get_register returns the value of a register whose offset from @regs. 235e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon * The @offset is the offset of the register in struct pt_regs. 236e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon * If @offset is bigger than MAX_REG_OFFSET, this returns 0. 237e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon */ 238e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deaconstatic inline unsigned long regs_get_register(struct pt_regs *regs, 239e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon unsigned int offset) 240e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon{ 241e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon if (unlikely(offset > MAX_REG_OFFSET)) 242e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon return 0; 243e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon return *(unsigned long *)((unsigned long)regs + offset); 244e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon} 245e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon 246e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon/* Valid only for Kernel mode traps. */ 247e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deaconstatic inline unsigned long kernel_stack_pointer(struct pt_regs *regs) 248e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon{ 249e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon return regs->ARM_sp; 250e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon} 251e513f8bf240d34bd6e732ba2f74df9ab84686ce6Will Deacon 252f22ab814a24e654b1de24db0c5f8b57b5ab2026aAdrian Bunk#endif /* __KERNEL__ */ 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* __ASSEMBLY__ */ 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 258